[coreboot-gerrit] [XS] Change in coreboot[main]: sb/intel/bd82x6x/pch: Mark static devices hidden

[Patrick Rudolph (Code Review)]

Attention is currently required from: Kyösti Mälkki.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78230?usp=email )

Change subject: sb/intel/bd82x6x/pch: Mark static devices hidden
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> My concern was about the enumeration process potentially assigning different bus numbers for S3 resu […]

All hot-pluggable PCIe root bridges use pciexp_hotplug_scan_bridge() to reserve a secondary-side bus number and resources.

I thought on S3 resume the ramstage is loaded from cache, but otherwise run as usual (cleared BSS). How can it contain a static entries from last boot?

Isn't the issue you describe something that the OS need to worry about?