[coreboot-gerrit] Change in coreboot[master]: [RFC] AMD APM_CNT and SMI enablement

[Felix Held (Code Review)]

Attention is currently required from: Marshall Dawson, Kyösti Mälkki.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42563 )

Change subject: [RFC] AMD APM_CNT and SMI enablement
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Patch Set 1:

(1 comment)

File src/soc/amd/picasso/southbridge.c:

https://review.coreboot.org/c/coreboot/+/42563/comment/9f1e7f32_58188a83 
PS1, Line 244: 	pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
> Now that I revisit this, PM1 and GPE0 sound like something chipset_power_state would need to eg. […]

without having looked into that, this sounds like a bug to me