[coreboot-gerrit] Change in coreboot[master]: xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices

[Marc Jones (Code Review)]

Attention is currently required from: Jonathan Zhang, Johnny Lin, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph, Tim Chu.
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49893 )

Change subject: xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices
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Patch Set 3:

(2 comments)

Patchset:

PS3: 
It seems odd that smbios stuff is being built in romstage, but that is a different patch...

File src/soc/intel/xeon_sp/cpx/romstage.c:

https://review.coreboot.org/c/coreboot/+/49893/comment/38d75428_c594aabe 
PS3, Line 24: uint32_t __weak mainboard_skt_memory_max_capacity_mib(void) { return 0; }
Does the really need a mainboard override? This should have a good default value for CPX.