[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add chip config for SATA strength

[Jamie Chen (Code Review)]

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38432 )

Change subject: soc/intel/cannonlake: Add chip config for SATA strength
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soc/intel/cannonlake: Add chip config for SATA strength

Add config to chip.h for tuning SATA gen3 strength.

Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e
Signed-off-by: Jamie Chen 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 30 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38432/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 07a67cd..54d1d70 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -390,6 +390,14 @@
    /* SATA Power Optimizer */
    uint8_t satapwroptimize;

+	/* SATA Gen3 Strength */
+	uint8_t PchSataHsioRxGen3EqBoostMagEnable[8];
+	uint8_t PchSataHsioRxGen3EqBoostMag[8];
+	uint8_t PchSataHsioTxGen3DownscaleAmpEnable[8];
+	uint8_t PchSataHsioTxGen3DownscaleAmp[8];
+	uint8_t PchSataHsioTxGen3DeEmphEnable[8];
+	uint8_t PchSataHsioTxGen3DeEmph[8];
+
    /* Enable or disable eDP device */
    uint8_t DdiPortEdp;

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 5c74d4a..8b7ac0e 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -101,6 +101,28 @@
    dev = pcidev_path_on_root(SA_DEVFN_IPU);
    if (dev)
    	m_cfg->SaIpuEnable = dev->enabled;
+
+	/* SATA Gen3 strength */
+	for (i = 0; i < 8; i++) {
+		if (config->PchSataHsioRxGen3EqBoostMagEnable[i]) {
+			m_cfg->PchSataHsioRxGen3EqBoostMagEnable[i] =
+				config->PchSataHsioRxGen3EqBoostMagEnable[i];
+			m_cfg->PchSataHsioRxGen3EqBoostMag[i] =
+				config->PchSataHsioRxGen3EqBoostMag[i];
+		}
+		if (config->PchSataHsioTxGen3DownscaleAmpEnable[i]) {
+			m_cfg->PchSataHsioTxGen3DownscaleAmpEnable[i] =
+				config->PchSataHsioTxGen3DownscaleAmpEnable[i];
+			m_cfg->PchSataHsioTxGen3DownscaleAmp[i] =
+				config->PchSataHsioTxGen3DownscaleAmp[i];
+		}
+		if (config->PchSataHsioTxGen3DeEmphEnable[i]) {
+			m_cfg->PchSataHsioTxGen3DeEmphEnable[i] =
+				config->PchSataHsioTxGen3DeEmphEnable[i];
+			m_cfg->PchSataHsioTxGen3DeEmph[i] =
+				config->PchSataHsioTxGen3DeEmph[i];
+		}
+	}
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)