Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69845 )
Change subject: UPSTREAM: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4 ......................................................................
UPSTREAM: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4
This change disables unused PCIE RP8 and CLKSRC4. Without this change sasukette cannot enter into s0ix properly.
BUG=b:259891452 TEST=Build and verified in sasukette
Change-Id: I1eb22c8c767006d0c2f8601c94705af9f4a61370 Signed-off-by: zhourui zhourui@huaqin.corp-partner.google.com --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/69845/1
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 1cda193..43a68db 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -8,6 +8,10 @@ end
chip soc/intel/jasperlake + # Disable PCIe Root Port 8 (index 7) + register "PcieRpEnable[7]" = "0" + # Disable PCIe Clock Source 4 (index 3) + register "PcieClkSrcUsage[3]" = "0xff"
# Intel Common SoC Config #+-------------------+---------------------------+