Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45408 )
Change subject: mb/ocp/deltalake: Override uart base address via VPD variable ......................................................................
mb/ocp/deltalake: Override uart base address via VPD variable
Use VPD of "uart_ioport" to override base address at run time, the data will be used during FSP/coreboot if UART_OVERRIDE_BASE_ADDR is selected.
Tested=On OCP Delta Lake, console messages correctly output to uart port which is defined in VPD.
Signed-off-by: Bryant Ou Bryant.Ou.Q@gmail.com Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc M src/mainboard/ocp/deltalake/romstage.c A src/mainboard/ocp/deltalake/uart.c M src/mainboard/ocp/deltalake/vpd.h 5 files changed, 66 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45408/1
diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index adce988..5671664 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -16,6 +16,7 @@ select IPMI_OCP select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 + select UART_OVERRIDE_BASE_ADDR
config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default n diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index be6af24..ecef891 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -8,5 +8,14 @@ ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+ifeq ($(CONFIG_UART_OVERRIDE_BASE_ADDR),y) +bootblock-y += uart.c +verstage-y += uart.c +romstage-y += uart.c +postcar-y += uart.c +ramstage-y += uart.c +smm-$(CONFIG_DEBUG_SMI) += uart.c +endif + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8..bf7491c 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -20,6 +20,8 @@ { uint8_t val; char val_str[VPD_LEN]; + uint16_t base; + char port[VPD_LEN];
/* Send FSP log message to SOL */ if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) @@ -29,7 +31,12 @@ "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; } - mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) + base = hex2int(port); + else + base = hex2int(UART_IOPORT_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugIoBase = base;
if (mupd->FspmConfig.SerialIoUartDebugEnable) { /* FSP debug log level */ diff --git a/src/mainboard/ocp/deltalake/uart.c b/src/mainboard/ocp/deltalake/uart.c new file mode 100644 index 0000000..28801c8 --- /dev/null +++ b/src/mainboard/ocp/deltalake/uart.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/uart.h> +#include <drivers/vpd/vpd.h> +#include <string.h> +#include "vpd.h" + +int hex2int(const char *hexstr) +{ + int val = 0; + + if (hexstr[0] == '0' && hexstr[1] == 'x') + hexstr = hexstr + 2; + + while (*hexstr) { + char c = *hexstr++; + if (c >= '0' && c <= '9') + c = c - '0'; + else if (c >= 'a' && c <='f') + c = c - 'a' + 10; + else if (c >= 'A' && c <='F') + c = c - 'A' + 10; + val = (val << 4) | (c & 0xF); + } + + return val; +} + +#if (CONFIG(UART_OVERRIDE_BASE_ADDR)) +uintptr_t uart_platform_base(unsigned int idx) +{ + char port[VPD_LEN]; + uintptr_t base; + + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) + base = hex2int(port); + else + base = hex2int(UART_IOPORT_DEFAULT); + + return base; +} +#endif \ No newline at end of file diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d..4285e68 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,10 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */
+/* Define uart io port for FSP/coreboot/payload */ +#define UART_IOPORT "uart_ioport" +#define UART_IOPORT_DEFAULT "0x2f8" + +int hex2int(const char *hexstr); + #endif