Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Todd Broch, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#16).
Change subject: tigerlake: update processor power limits configuration ......................................................................
tigerlake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None BUG=None TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl A src/soc/intel/common/acpi/dptf.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/systemagent.c 13 files changed, 217 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/16