Attention is currently required from: Karthikeyan Ramasubramanian. Hello Karthikeyan Ramasubramanian,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/51509
to review the following change.
Change subject: soc/amd/common/block/i2c: Move SoC agnostic parts into common ......................................................................
soc/amd/common/block/i2c: Move SoC agnostic parts into common
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers.
BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen.
Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Suggested-by: Kyosti Malkki kyosti.malkki@gmail.com --- M src/mainboard/google/kahlee/mainboard.c M src/soc/amd/common/block/i2c/i2c.c M src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/i2c.c M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 11 files changed, 222 insertions(+), 225 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/51509/1
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ad38b2d..c44da75 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -7,6 +7,7 @@ #include <acpi/acpi.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/i2c.h> #include <baseboard/variants.h> #include <boardid.h> #include <smbios.h> diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c index 7b47deb..ffefd0b 100644 --- a/src/soc/amd/common/block/i2c/i2c.c +++ b/src/soc/amd/common/block/i2c/i2c.c @@ -1,14 +1,119 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <assert.h> -#include <delay.h> #include <amdblocks/acpimmio.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/gpio_defs.h> #include <amdblocks/i2c.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/mmio.h> +#include <drivers/i2c/designware/dw_i2c.h>
#define MAX_PIN_COUNT 4
+uintptr_t dw_i2c_base_address(unsigned int bus) +{ + struct soc_amd_i2c_bar_config config; + + soc_amd_get_i2c_bar_config(&config); + if (bus >= config.num_bars) + return 0; + + return config.i2c_bar_acpi_map[bus].bar; +} + +const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) +{ + struct soc_amd_i2c_config config; + + soc_amd_get_i2c_config(&config); + if (bus >= config.num_i2c_buses) + return NULL; + + return &config.i2c[bus]; +} + +static const char *i2c_acpi_name(const struct device *dev) +{ + size_t i; + struct soc_amd_i2c_bar_config config; + + if (!(uintptr_t)dev->path.mmio.addr) + return NULL; + + soc_amd_get_i2c_bar_config(&config); + for (i = 0; i < config.num_bars; i++) { + if ((uintptr_t)dev->path.mmio.addr == config.i2c_bar_acpi_map[i].bar) + return config.i2c_bar_acpi_map[i].acpi_name; + } + return NULL; +} + +int dw_i2c_soc_dev_to_bus(const struct device *dev) +{ + size_t i; + struct soc_amd_i2c_bar_config config; + + if (!(uintptr_t)dev->path.mmio.addr) + return -1; + + soc_amd_get_i2c_bar_config(&config); + for (i = 0; i < config.num_bars; i++) { + if ((uintptr_t)dev->path.mmio.addr == config.i2c_bar_acpi_map[i].bar) + return i; + } + return -1; +} + +__weak void soc_amd_i2c_misc_init(unsigned int bus, enum i2c_speed speed) +{ + /* Nothing by default. */ +} + +static void dw_i2c_soc_init(bool is_early_init) +{ + size_t i; + struct soc_amd_i2c_config config; + + soc_amd_get_i2c_config(&config); + for (i = config.i2c_bus_start_index; i < config.num_i2c_buses; i++) { + const struct dw_i2c_bus_config *cfg = &config.i2c[i]; + + if (cfg->early_init != is_early_init) + continue; + + if (dw_i2c_init(i, cfg)) { + printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); + continue; + } + + soc_amd_i2c_misc_init(i, cfg->speed); + } +} + +void i2c_soc_early_init(void) +{ + dw_i2c_soc_init(true); +} + +void i2c_soc_init(void) +{ + dw_i2c_soc_init(false); +} + +struct device_operations soc_amd_i2c_mmio_ops = { + /* TODO(teravest): Move I2C resource info here. */ + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_smbus, + .acpi_name = i2c_acpi_name, + .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, +}; + struct soc_amd_i2c_save { uint32_t control_value; uint8_t mux_value; diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h index 7c9cfed..880c52a 100644 --- a/src/soc/amd/common/block/include/amdblocks/i2c.h +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -1,11 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <types.h> +#include <acpi/acpi.h> #include <amdblocks/gpio_banks.h> +#include <device/i2c.h> +#include <types.h>
#ifndef AMD_COMMON_BLOCK_I2C_H #define AMD_COMMON_BLOCK_I2C_H
+struct soc_amd_i2c_bar_acpi_map { + uintptr_t bar; + char acpi_name[ACPI_NAME_BUFFER_SIZE]; +}; + +/** + * Data structure to get I2C base address configuration + * @i2c_bar_acpi_map: I2C base address to ACPI name map. + * @num_bars: Number of I2C base addresses in the configuration. + */ +struct soc_amd_i2c_bar_config { + const struct soc_amd_i2c_bar_acpi_map *i2c_bar_acpi_map; + size_t num_bars; +}; + +/** + * Data structure to get SoC specific I2C bus configuration + * @i2c: Array of I2C bus configuration as configured in devicetree. + * @i2c_bus_start_index: Index of the first usable I2C bus within @i2c. + * @num_i2c_buses: Total number of I2C buses in the configuration array. + */ +struct soc_amd_i2c_config { + const struct dw_i2c_bus_config *i2c; + size_t i2c_bus_start_index; + size_t num_i2c_buses; +}; + struct soc_amd_i2c_scl_pin { struct soc_amd_gpio pin; uint8_t pin_mask; @@ -26,6 +55,21 @@ uint32_t num_pins; };
+/* Helper function to perform misc I2C configuration specific to SoC. */ +void soc_amd_i2c_misc_init(unsigned int bus, enum i2c_speed speed); + +/* Getter function to get the SoC I2C base address configuration. */ +void soc_amd_get_i2c_bar_config(struct soc_amd_i2c_bar_config *cfg); + +/* Getter function to get the SoC I2C bus configuration. */ +void soc_amd_get_i2c_config(struct soc_amd_i2c_config *cfg); + +/* Initialize all the i2c buses that are marked with early init. */ +void i2c_soc_early_init(void); + +/* Initialize all the i2c buses that are not marked with early init. */ +void i2c_soc_init(void); + /** * Get information about I2C peripherals that need to be reset. * @reset_info: In/Out parameter for the SoC specific I2C driver to populate diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 9f9ca24..6a6c49e 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -14,7 +14,7 @@ #include <fsp/api.h>
/* Supplied by i2c.c */ -extern struct device_operations picasso_i2c_mmio_ops; +extern struct device_operations soc_amd_i2c_mmio_ops; /* Supplied by uart.c */ extern struct device_operations picasso_uart_mmio_ops;
@@ -51,7 +51,7 @@ case APU_I2C2_BASE: case APU_I2C3_BASE: case APU_I2C4_BASE: - dev->ops = &picasso_i2c_mmio_ops; + dev->ops = &soc_amd_i2c_mmio_ops; break; case APU_UART0_BASE: case APU_UART1_BASE: diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index e52090a..4568e20 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -13,6 +13,7 @@ #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> +#include <amdblocks/i2c.h> #include <amdblocks/smi.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 10de4a6..dfce9f4 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/mmio.h> -#include <acpi/acpi.h> #include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> #include <amdblocks/i2c.h> #include <soc/i2c.h> @@ -15,133 +10,67 @@ #include "chip.h"
#if ENV_X86 -static const uintptr_t i2c_bus_address[I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT] = { - 0, - 0, - APU_I2C2_BASE, - APU_I2C3_BASE, - APU_I2C4_BASE, /* Can only be used in slave mode */ +static const struct soc_amd_i2c_bar_acpi_map + i2c_bar[I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT] = { + { 0, "" }, + { 0, "" }, + { APU_I2C2_BASE, "I2C2" }, + { APU_I2C3_BASE, "I2C3" }, + { APU_I2C4_BASE, "I2C4" } /* Can only be used in slave mode */ }; #else -static uintptr_t i2c_bus_address[I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT]; -#endif +static struct soc_amd_i2c_bar_acpi_map i2c_bar[I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT];
-uintptr_t dw_i2c_base_address(unsigned int bus) -{ - if (bus >= ARRAY_SIZE(i2c_bus_address)) - return 0; - - return i2c_bus_address[bus]; -} - -#if !ENV_X86 void i2c_set_bar(unsigned int bus, uintptr_t bar) { - if (bus >= ARRAY_SIZE(i2c_bus_address)) { + if (bus >= ARRAY_SIZE(i2c_bar)) { printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); return; }
- i2c_bus_address[bus] = bar; + i2c_bar[bus].bar = bar; } #endif
-const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) -{ - const struct soc_amd_picasso_config *config; - - if (bus >= ARRAY_SIZE(config->i2c)) - return NULL; - - /* config is not NULL; if it was, config_of_soc calls die() internally */ - config = config_of_soc(); - - return &config->i2c[bus]; -} - -static const char *i2c_acpi_name(const struct device *dev) -{ - if ((uintptr_t)dev->path.mmio.addr == i2c_bus_address[2]) - return "I2C2"; - else if ((uintptr_t)dev->path.mmio.addr == i2c_bus_address[3]) - return "I2C3"; - else if ((uintptr_t)dev->path.mmio.addr == i2c_bus_address[4]) - return "I2C4"; - return NULL; -} - -int dw_i2c_soc_dev_to_bus(const struct device *dev) -{ - if ((uintptr_t)dev->path.mmio.addr == i2c_bus_address[2]) - return 2; - else if ((uintptr_t)dev->path.mmio.addr == i2c_bus_address[3]) - return 3; - else if ((uintptr_t)dev->path.mmio.addr == i2c_bus_address[4]) - return 4; - return -1; -} - __weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { }
-static void dw_i2c_soc_init(bool is_early_init) +void soc_amd_i2c_misc_init(unsigned int bus, enum i2c_speed speed) { - size_t i; - const struct soc_amd_picasso_config *config; uint32_t pad_ctrl; int misc_reg;
- /* config is not NULL; if it was, config_of_soc calls die() internally */ - config = config_of_soc(); + misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus; + pad_ctrl = misc_read32(misc_reg);
- for (i = I2C_MASTER_START_INDEX; i < ARRAY_SIZE(config->i2c); i++) { - const struct dw_i2c_bus_config *cfg = &config->i2c[i]; + pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; + pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
- if (cfg->early_init != is_early_init) - continue; + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V;
- if (dw_i2c_init(i, cfg)) { - printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); - continue; - } + pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; + pad_ctrl |= speed == I2C_SPEED_STANDARD ? I2C_PAD_CTRL_FALLSLEW_STD : + I2C_PAD_CTRL_FALLSLEW_LOW; + pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
- misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * i; - pad_ctrl = misc_read32(misc_reg); - - pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; - pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; - - pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; - pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; - - pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; - pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD - ? I2C_PAD_CTRL_FALLSLEW_STD - : I2C_PAD_CTRL_FALLSLEW_LOW; - pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - - mainboard_i2c_override(i, &pad_ctrl); - misc_write32(misc_reg, pad_ctrl); - } + mainboard_i2c_override(bus, &pad_ctrl); + misc_write32(misc_reg, pad_ctrl); }
-void i2c_soc_early_init(void) +void soc_amd_get_i2c_bar_config(struct soc_amd_i2c_bar_config *cfg) { - dw_i2c_soc_init(true); + cfg->i2c_bar_acpi_map = i2c_bar; + cfg->num_bars = ARRAY_SIZE(i2c_bar); }
-void i2c_soc_init(void) +void soc_amd_get_i2c_config(struct soc_amd_i2c_config *i2c_cfg) { - dw_i2c_soc_init(false); -} + const struct soc_amd_picasso_config *soc_config = config_of_soc();
-struct device_operations picasso_i2c_mmio_ops = { - /* TODO(teravest): Move I2C resource info here. */ - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .scan_bus = scan_smbus, - .acpi_name = i2c_acpi_name, - .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, -}; + i2c_cfg->i2c = soc_config->i2c; + i2c_cfg->i2c_bus_start_index = I2C_MASTER_START_INDEX; + i2c_cfg->num_i2c_buses = ARRAY_SIZE(soc_config->i2c); +}
/* This table is for the initial conversion of all SCL pins to input with no pull. */ static const struct soc_amd_i2c_scl_pin i2c_scl_pins[] = { diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 60fd6f9..49e4948 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -181,12 +181,6 @@ void wait_for_aoac_enabled(unsigned int dev); void sb_clk_output_48Mhz(void);
-/* Initialize all the i2c buses that are marked with early init. */ -void i2c_soc_early_init(void); - -/* Initialize all the i2c buses that are not marked with early init. */ -void i2c_soc_init(void); - /* Allow the board to change the default I2C pad configuration */ void mainboard_i2c_override(int bus, uint32_t *pad_settings);
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 8082165..73f2086 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -14,12 +14,12 @@ #include <amdblocks/psp.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include <amdblocks/i2c.h>
#include "chip.h"
/* Supplied by i2c.c */ -extern struct device_operations stoneyridge_i2c_mmio_ops; -extern const char *i2c_acpi_name(const struct device *dev); +extern struct device_operations soc_amd_i2c_mmio_ops;
struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, @@ -98,6 +98,18 @@ .acpi_name = soc_acpi_name, };
+static void set_mmio_dev_ops(struct device *dev) +{ + switch (dev->path.mmio.addr) { + case I2CA_BASE_ADDRESS: + case I2CB_BASE_ADDRESS: + case I2CC_BASE_ADDRESS: + case I2CD_BASE_ADDRESS: + dev->ops = &soc_amd_i2c_mmio_ops; + break; + } +} + static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ @@ -109,8 +121,7 @@ dev->ops = &cpu_bus_ops; break; case DEVICE_PATH_MMIO: - if (i2c_acpi_name(dev) != NULL) - dev->ops = &stoneyridge_i2c_mmio_ops; + set_mmio_dev_ops(dev); break; default: break; diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index c90ede9..44f3d17 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -1,122 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/mmio.h> -#include <acpi/acpi.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> #include <amdblocks/i2c.h> #include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/southbridge.h> #include <soc/i2c.h> #include "chip.h"
-#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) -#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) -#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) -#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) -#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) - -/* Global to provide access to chip.c */ -const char *i2c_acpi_name(const struct device *dev); - -static const uintptr_t i2c_bus_address[] = { - I2CA_BASE_ADDRESS, - I2CB_BASE_ADDRESS, - I2CC_BASE_ADDRESS, - I2CD_BASE_ADDRESS, +static const struct soc_amd_i2c_bar_acpi_map i2c_bar[] = { + { I2CA_BASE_ADDRESS, "I2CA" }, + { I2CB_BASE_ADDRESS, "I2CB" }, + { I2CC_BASE_ADDRESS, "I2CC" }, + { I2CD_BASE_ADDRESS, "I2CD" }, };
-uintptr_t dw_i2c_base_address(unsigned int bus) +void soc_amd_get_i2c_bar_config(struct soc_amd_i2c_bar_config *cfg) { - return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; + cfg->i2c_bar_acpi_map = i2c_bar; + cfg->num_bars = ARRAY_SIZE(i2c_bar); }
-const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) +void soc_amd_get_i2c_config(struct soc_amd_i2c_config *i2c_cfg) { - const struct soc_amd_stoneyridge_config *config; + const struct soc_amd_stoneyridge_config *soc_config = config_of_soc();
- if (bus >= ARRAY_SIZE(i2c_bus_address)) - return NULL; - - /* config is not NULL; if it was, config_of_soc calls die() internally */ - config = config_of_soc(); - - return &config->i2c[bus]; + i2c_cfg->i2c = soc_config->i2c; + i2c_cfg->i2c_bus_start_index = 0; + i2c_cfg->num_i2c_buses = ARRAY_SIZE(soc_config->i2c); }
-const char *i2c_acpi_name(const struct device *dev) -{ - switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return "I2CA"; - case I2CB_BASE_ADDRESS: - return "I2CB"; - case I2CC_BASE_ADDRESS: - return "I2CC"; - case I2CD_BASE_ADDRESS: - return "I2CD"; - default: - return NULL; - } -} - -int dw_i2c_soc_dev_to_bus(const struct device *dev) -{ - switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return 0; - case I2CB_BASE_ADDRESS: - return 1; - case I2CC_BASE_ADDRESS: - return 2; - case I2CD_BASE_ADDRESS: - return 3; - } - return -1; -} - -static void dw_i2c_soc_init(bool is_early_init) -{ - size_t i; - const struct soc_amd_stoneyridge_config *config; - - /* config is not NULL; if it was, config_of_soc calls die() internally */ - config = config_of_soc(); - - for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { - const struct dw_i2c_bus_config *cfg = &config->i2c[i]; - - if (cfg->early_init != is_early_init) - continue; - - if (dw_i2c_init(i, cfg)) - printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); - } -} - -void i2c_soc_early_init(void) -{ - dw_i2c_soc_init(true); -} - -void i2c_soc_init(void) -{ - dw_i2c_soc_init(false); -} - -struct device_operations stoneyridge_i2c_mmio_ops = { - /* TODO(teravest): Move I2C resource info here. */ - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .scan_bus = scan_smbus, - .acpi_name = i2c_acpi_name, - .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, -}; - /* This table is for the initial conversion of all SCL pins to input with no pull. */ static const struct soc_amd_i2c_scl_pin i2c_scl_pins[] = { { PAD_GPI(I2C0_SCL_PIN, PULL_NONE), GPIO_I2C0_SCL }, diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 7832dad..688eb94 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -15,6 +15,13 @@ #define I2C_DEVICE_SIZE 0x00001000 #define I2C_DEVICE_COUNT 4
+#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) +#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) +#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) +#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) +#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) + + #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 #endif diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9480e8b..8aa881b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -250,10 +250,4 @@ int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map);
-/* Initialize all the i2c buses that are marked with early init. */ -void i2c_soc_early_init(void); - -/* Initialize all the i2c buses that are not marked with early init. */ -void i2c_soc_init(void); - #endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */