[coreboot-gerrit] Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram

[Subrata Banik (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Aaron Durbin, David Guckian, Vanny E, Kane Chen, Aamir Bohra, V Sowmya, build bot (Jenkins), David Guckian, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34995

to look at the new patch set (#10).

Change subject: arch/x86: Cache the TSEG region at the top of ram
......................................................................

arch/x86: Cache the TSEG region at the top of ram

This patch adds new API for enabling caching for the TSEG region
and setting up required MTRR for next stage.

Also removes dedicated function call to make TSEG region cache
from soc and refers to enable_tseg_cache().

BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot

Without this CL :
Total Time: 929ms

With this CL : (TSEG marked as WB)
Total Time: 910ms

For test marked TSEG as WP/WC :
Total Time: ~920ms

Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb
Signed-off-by: Subrata Banik 
---
M src/arch/x86/postcar_loader.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/skylake/memmap.c
6 files changed, 24 insertions(+), 60 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34995/10