Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... File src/soc/rockchip/rk3399/include/soc/memlayout.ld:
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 23: 16M
Why would this need to change?
I forget exactly, but someone mentioned increasing/adding a POSTRAM_CBFS_CACHE, see src/soc/cavium/cn81xx/include/soc/memlayout.ld:51
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 24: 1100000
Why change the base address? (2M would've still easily fit where it was before. […]
Unless I'm mistaken, the first parameter is an address in 'normal' dram and they're sequential (BL31 starts at 0 and extends 0x100000 bytes, and POSTRAM_CBFS_CACHE starts at 0x100000, the end of BL31, so I added 16*1024*1024 to the starting address of POSTRAM_CBFS_CACHE and 'moved' the RAMSTAGE there.