HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16924
-gerrit
commit d3a64470c652d0887f8bf2d35c7664b43b785052 Author: Elyes HAOUAS ehaouas@noos.fr Date: Fri Oct 7 17:41:34 2016 +0200
mainboard/asrock: Use C89 comments style & remove commented code
Change-Id: Ib9dc94675a8ca5bafc29d1f883229bce6f08a325 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 2 +- src/mainboard/asrock/e350m1/OemCustomize.c | 17 ++- .../asrock/e350m1/PlatformGnbPcieComplex.h | 83 +++++++------ src/mainboard/asrock/e350m1/mainboard.c | 1 - src/mainboard/asrock/e350m1/mptable.c | 3 +- src/mainboard/asrock/e350m1/platform_cfg.h | 1 - src/mainboard/asrock/imb-a180/BiosCallOuts.c | 17 ++- src/mainboard/asrock/imb-a180/OptionsIds.h | 10 -- src/mainboard/asrock/imb-a180/buildOpts.c | 128 +++++---------------- src/mainboard/asrock/imb-a180/mptable.c | 4 - src/mainboard/asrock/imb-a180/romstage.c | 2 - 11 files changed, 84 insertions(+), 184 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 2e86ff6..26b92a6 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -117,7 +117,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); } - // disable memory clear for boot time reduction + /* disable memory clear for boot time reduction */ MemData->ParameterListPtr->EnableMemClr = FALSE; return Status; } diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index ab563ae..7f300ab 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -52,13 +52,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -67,18 +67,16 @@ PCIe_PORT_DESCRIPTOR PortList [] = { };
PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeDP, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -90,11 +88,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] };
- // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
- // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 001ed16..77b79b9 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -20,45 +20,44 @@ #include "AGESA.h" #include "amdlib.h"
-//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 452d50f..5c7848f 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -23,7 +23,6 @@ #include <southbridge/amd/cimx/cimx_util.h> #include "SBPLATFORM.h"
-//#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); void set_pcie_dereset(void);
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index eef3554..349b448 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */
- #include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> @@ -84,7 +83,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 5e93dc1..bf7934a 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -161,7 +161,6 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A
/** diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index e7958e9..25adf02 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -180,8 +180,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; /* BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;/* 6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -192,7 +192,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -217,7 +217,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;/* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -252,7 +252,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;/* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -263,7 +263,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;/* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -273,7 +273,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
/* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8; */
/* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -303,7 +303,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { @@ -315,7 +315,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) /* Azalia Controller Front Panel OEM Table Pointer */
/* Fan Control */ - //oem_fan_control(FchParams_env);
/* XHCI configuration */ FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/asrock/imb-a180/OptionsIds.h b/src/mainboard/asrock/imb-a180/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/asrock/imb-a180/OptionsIds.h +++ b/src/mainboard/asrock/imb-a180/OptionsIds.h @@ -43,17 +43,7 @@ **/
#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 07431e3..99310de 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -53,36 +53,22 @@ #endif #endif
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
-//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -104,11 +90,11 @@ #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the */ + /* core for C-state entry requests. A value */ + /* of 0 in this field specifies that the core */ + /* does not trap any IO addresses for C-state entry. */ + /* Values greater than 0xFFF8 results in undefined behavior. */ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -149,15 +135,10 @@ #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
#ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS @@ -174,43 +155,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -244,40 +188,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* QUANDRANK_TYPE*/ + +/* USER_MEMORY_TIMING_MODE */ + +/* POWER_DOWN_MODE */
/* * Agesa optional capabilities selection. @@ -322,17 +247,16 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL imba180_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
-// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 6241282..4ff8ea1 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -82,7 +82,6 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -113,9 +112,6 @@ static void *smp_write_config_table(void *v) outb(0x48, 0xCD6); outb(0xF2, 0xCD7);
- //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - outb(0xED, 0xCD6); outb(0x17, 0xCD7);
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 7070e69..afad58a 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -48,8 +48,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ - //outb(0xD2, 0xcd6); - //outb(0x00, 0xcd7);
amd_initmmio();