[coreboot-gerrit] Change in ...coreboot[master]: soc/intel: Drop soc_uart_set_legacy_mode() implementations

[Nico Huber (Code Review)]

Hello Patrick Rudolph, Lance Zhao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/33093

to review the following change.

Change subject: soc/intel: Drop soc_uart_set_legacy_mode() implementations
......................................................................

soc/intel: Drop soc_uart_set_legacy_mode() implementations

They are never called: The only calling path is guarded by both
!DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the
latter selects the former.

If somebody figures out how this is supposed to be used, we can
easily revive the implementation.

Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307
Signed-off-by: Nico Huber 
---
M src/soc/intel/cannonlake/uart.c
M src/soc/intel/icelake/uart.c
M src/soc/intel/skylake/uart.c
3 files changed, 0 insertions(+), 45 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33093/1

diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 2bd906a..7174a9a 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -24,10 +24,6 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>

-/* Serial IO UART controller legacy mode */
-#define PCR_SERIAL_IO_GPPRVRW7		0x618
-#define PCR_SIO_PCH_LEGACY_UART(idx)	(1 << (idx))
-
 const struct uart_gpio_pad_config uart_gpio_pads[] = {
    {
    	.console_index = 0,
@@ -54,17 +50,6 @@

const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);

-void soc_uart_set_legacy_mode(void)
-{
-	pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
-		PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
-	/*
-	 * Dummy read after setting any of GPPRVRW7.
-	 * Required for UART 16550 8-bit Legacy mode to become active
-	 */
-	lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
-}
-
 struct device *soc_uart_console_to_device(int uart_console)
 {
    /*
diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c
index 2bd906a..7174a9a 100644
--- a/src/soc/intel/icelake/uart.c
+++ b/src/soc/intel/icelake/uart.c
@@ -24,10 +24,6 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>

-/* Serial IO UART controller legacy mode */
-#define PCR_SERIAL_IO_GPPRVRW7		0x618
-#define PCR_SIO_PCH_LEGACY_UART(idx)	(1 << (idx))
-
 const struct uart_gpio_pad_config uart_gpio_pads[] = {
    {
    	.console_index = 0,
@@ -54,17 +50,6 @@

const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);

-void soc_uart_set_legacy_mode(void)
-{
-	pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
-		PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
-	/*
-	 * Dummy read after setting any of GPPRVRW7.
-	 * Required for UART 16550 8-bit Legacy mode to become active
-	 */
-	lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
-}
-
 struct device *soc_uart_console_to_device(int uart_console)
 {
    /*
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 1b2a742..8b7c99e 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -24,10 +24,6 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>

-/* Serial IO UART controller legacy mode */
-#define PCR_SERIAL_IO_GPPRVRW7		0x618
-#define PCR_SIO_PCH_LEGACY_UART(idx)	(1 << (idx))
-
 /* UART pad configuration. Support RXD and TXD for now. */
 const struct uart_gpio_pad_config uart_gpio_pads[] = {
    {
@@ -55,17 +51,6 @@

const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);

-void soc_uart_set_legacy_mode(void)
-{
-	pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
-		PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
-	/*
-	 * Dummy read after setting any of GPPRVRW7.
-	 * Required for UART 16550 8-bit Legacy mode to become active
-	 */
-	lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
-}
-
 struct device *soc_uart_console_to_device(int uart_console)
 {
    /*