Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23793
Change subject: soc/cavium: Add rom header images ......................................................................
soc/cavium: Add rom header images
Add HEX rom header images, required to boot NBL1FW.
Change-Id: Icd9cdf882ccdac591bec7240f1c7694fe0c0ad4d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/cavium/cn81xx/Makefile.inc M src/soc/cavium/common/Makefile.inc A src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex A src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex 4 files changed, 53 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/23793/1
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index f835b09..c910b08 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -97,29 +97,4 @@ CPPFLAGS_common += -Isrc/soc/cavium/common/include/soc/bdk/ #CPPFLAGS_common += -Isrc/soc/cavium/common/include/soc/bdk/libdram
-# FIXME: Generate the ROM code load information block structure. -# For NBL1FW the first 256 bytes are ignored and should be zeros. -# For TLB1FW the first 256 bytes should be randomized. -#FIXME: Generate bootblock more intelligently -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin - @printf "Generating: $(subst $(obj)/,,$(@))\n" -# cp $< $@ -# @mkdir -p $(dir $@) -# @$(IBSTOOL) --from=$< --to=$@ --nontrusted - # Insert CLIB at 0x10000 and CSIB at 0x10100 -# dd if=/dev/zero bs=1k count=512 2>/dev/null | tr '\000' '\377' > $@ - dd if=rom_clib_s_nbl1fw.bin of=$@ bs=1 seek=$$((0x10000)) conv=notrunc - dd if=rom_csib_s_nbl1fw.bin of=$@ bs=1 seek=$$((0x10100)) conv=notrunc - # Insert header at 0x20000 -# According to OFFSET field description, first 256 bytes of NBL1FW are ignored. -# dd if=/dev/zero bs=1 count=256 2>/dev/null | tr '\000' '\377' > _pad256.bin - - # FIXME: 0x20000-0x20100 should be ignored, but Cavium's image populates it. - ## dd if=_pad256.bin of=$@ bs=1 seek=$$((0x20000)) conv=notrunc 2>/dev/null - # TODO inject length of firmware at offset 0x04 of header - ##dd if=$< of=$@ bs=1 seek=$$((0x20100)) conv=notrunc 2>/dev/null - dd if=$< of=$@ bs=1 seek=$$((0x20000)) conv=notrunc -# dd if=nbl1fw_header.bin of=$@ bs=1 seek=$$((0x20000)) conv=notrunc -# # TODO: Calculate CRC32 of image and inject at offset 0x10 of header - endif diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc index feeeb6e..5f47a1d 100644 --- a/src/soc/cavium/common/Makefile.inc +++ b/src/soc/cavium/common/Makefile.inc @@ -45,4 +45,25 @@
CPPFLAGS_common += -Isrc/soc/cavium/common/include
+ROM_HEADER_BIN := $(objgenerated)/rom_header.bin +ROM_HEADER_SOURCES += rom_clib_s_nbl1fw +ROM_HEADER_SOURCES += rom_csib_s_nbl1fw + +ROM_HEADER_DEPS := $(foreach f, $(ROM_HEADER_SOURCES), src/soc/cavium/common/$(f).bin.hex) + +# Include ROM header +$(ROM_HEADER_BIN): $(ROM_HEADER_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '%o' 0x$$c); \ + done; \ + done > $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(ROM_HEADER_BIN) + @printf " GEN $(subst $(obj)/,,$(@))\n" + # Insert CLIB at 0x10000 and CSIB at 0x10100 + dd if=$(ROM_HEADER_BIN) of=$@ bs=1 seek=$$((0x10000)) conv=notrunc status=none + # Insert bootblock at 0x20000 + dd if=$(objcbfs)/bootblock.raw.bin of=$@ bs=1 seek=$$((0x20000)) conv=notrunc status=none + endif diff --git a/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex b/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex new file mode 100644 index 0000000..231c6a6 --- /dev/null +++ b/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex @@ -0,0 +1,16 @@ +43 56 4d 5f 43 4c 49 42 00 00 00 00 00 00 00 00 +00 00 02 00 00 00 00 00 00 00 03 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex b/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex new file mode 100644 index 0000000..f7a2021 --- /dev/null +++ b/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex @@ -0,0 +1,16 @@ +43 56 4d 5f 43 53 49 42 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00