Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44087 )
Change subject: [DO NOT MERGE] moar q1900m fixups ......................................................................
[DO NOT MERGE] moar q1900m fixups
Change-Id: I10b733c147854025a15ccdb4742ff3e76b4a7184 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/q1900m/irqroute.h M src/mainboard/asrock/q1900m/romstage.c M src/soc/intel/baytrail/sata.c 3 files changed, 37 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44087/1
diff --git a/src/mainboard/asrock/q1900m/irqroute.h b/src/mainboard/asrock/q1900m/irqroute.h index bc6c071..72a29c3 100644 --- a/src/mainboard/asrock/q1900m/irqroute.h +++ b/src/mainboard/asrock/q1900m/irqroute.h @@ -8,7 +8,7 @@ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ @@ -29,19 +29,3 @@ PIRQ_PIC(F, DISABLE), \ PIRQ_PIC(G, DISABLE), \ PIRQ_PIC(H, DISABLE) - -/* CORE bank DIRQs - up to 16 supported */ -//#define TPAD_IRQ_OFFSET 0 -//#define TOUCH_IRQ_OFFSET 1 -//#define I8042_IRQ_OFFSET 2 -//#define ALS_IRQ_OFFSET 3 -/* Corresponding SCORE GPIO pins */ -//#define TPAD_IRQ_GPIO 55 -//#define TOUCH_IRQ_GPIO 72 -//#define I8042_IRQ_GPIO 101 -//#define ALS_IRQ_GPIO 70 - -/* SUS bank DIRQs - up to 16 supported */ -//#define CODEC_IRQ_OFFSET 0 -/* Corresponding SUS GPIO pins */ -//#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/asrock/q1900m/romstage.c b/src/mainboard/asrock/q1900m/romstage.c index 0d48149..1d1bec9 100644 --- a/src/mainboard/asrock/q1900m/romstage.c +++ b/src/mainboard/asrock/q1900m/romstage.c @@ -1,18 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h> -#include <string.h> -#include <cbfs.h> #include <console/console.h> +#include <device/pci_ops.h> #include <device/pnp_ops.h> -#include <soc/gpio.h> +#include <device/smbus_host.h> +#include <soc/gfx.h> #include <soc/mrc_wrapper.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+static uint8_t spd[2][256]; + void mainboard_fill_mrc_params(struct mrc_params *mp) { /* Enable UART */ @@ -21,33 +24,30 @@ /* I'm a bit desperate. */ printk(BIOS_EMERG, "AAAAAAAA WE LIVEEEEEEEEEE\n");
- uint8_t spd[2][256]; - uint8_t *spd_raw; - size_t spd_fsize; - mp->mainboard.dram_type = DRAM_DDR3; mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; - //mp->mainboard.weaker_odt_settings = 1; mp->mainboard.dram_is_slotted = 1; - mp->mainboard.spd_addrs[0] = 0xf0; - mp->mainboard.spd_addrs[1] = 0; // 0xf1;
- spd_raw = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); + /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ + enable_smbus(); + i2c_eeprom_read(0x50, 0, sizeof(spd[0]), spd[0]); + i2c_eeprom_read(0x52, 0, sizeof(spd[1]), spd[1]);
- if (!spd_raw) - die("SPD data not found."); - - memcpy(&spd[0], spd_raw, 256); - memcpy(&spd[1], spd_raw, 256); - -#if 0 + /* Patch memory type and voltage settings to make MRC happy */ spd[0][3] = 0x03; spd[1][3] = 0x03;
spd[0][6] = 0x02; spd[1][6] = 0x02; -#endif
- mp->mainboard.dram_data[0] = spd_raw; - mp->mainboard.dram_data[1] = spd_raw; + mp->mainboard.dram_data[0] = spd; + mp->mainboard.dram_data[1] = spd; + + const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC); + + uint32_t ggc = pci_read_config32(gfx_dev, GGC); + + ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); + ggc |= GGC_GTT_SIZE_2MB | (0xf << 3); + pci_write_config32(gfx_dev, GGC, ggc); } diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 4dc3ea4..cf1b21e 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -47,6 +47,11 @@ reg16 = pci_read_config16(dev, 0x70); reg16 &= ~0xFF00; pci_write_config16(dev, 0x70, reg16); + + } else { + reg16 = pci_read_config16(dev, 0x90); + reg16 |= 7 << 5; + pci_write_config16(dev, 0x90, reg16); }
/* Primary timing - decode enable */ @@ -61,17 +66,22 @@
/* Port mapping enables */ reg16 = pci_read_config16(dev, 0x90); + reg16 &= ~0x0300; reg16 |= (config->sata_port_map ^ 0x3) << 8; pci_write_config16(dev, 0x90, reg16);
/* Port control enables */ reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x003f; + reg16 &= ~0x0003; + reg16 |= (1 << 15); reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); + udelay(2);
if (config->sata_ahci) { - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + + printk(BIOS_DEBUG, "SATA: ABAR at %#8x\n", (u32)abar);
/* Enable CR memory space decoding */ reg16 = pci_read_config16(dev, 0x04); @@ -83,11 +93,13 @@ reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits reg32 |= (0x3 << 20); // Gen3 SATA + reg32 |= (1 << 30); + reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ write32(abar + 0x00, reg32);
/* Ports enabled */ reg32 = read32(abar + 0x0c); - reg32 &= (u32)(~0x3f); + reg32 &= (u32)(~0x03); reg32 |= config->sata_port_map; write32(abar + 0xc, reg32); /* Two extra reads to latch */