Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35146 )
Change subject: intel/quark: Use common romstage entry ......................................................................
intel/quark: Use common romstage entry
Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/quark/romstage/Makefile.inc M src/soc/intel/quark/romstage/fsp2_0.c 2 files changed, 2 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index be5b320..13963d4 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -22,5 +22,6 @@ romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c
postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index b3f3ee8..6e23de7 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */
-#include <arch/cpu.h> #include <arch/romstage.h> #include <arch/symbols.h> #include <console/console.h> @@ -28,9 +27,7 @@ #include <soc/reg_access.h> #include <soc/storage_test.h>
-static struct postcar_frame early_mtrrs; - -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake;
@@ -61,9 +58,6 @@
/* Initialize the PCIe bridges */ pcie_init(); - - prepare_and_run_postcar(&early_mtrrs); - /* We do not return here. */ }
static struct chipset_power_state power_state;