[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36519 )

Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating
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Patch Set 13: Code-Review+2

(2 comments)

https://review.coreboot.org/c/coreboot/+/36519/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36519/3//COMMIT_MSG@9 
PS3, Line 9: Workaround for an issue seen when a specific charger is connected while
           : in S0ix state
> Which charger?  What was the issue that this solves?

Ack

https://review.coreboot.org/c/coreboot/+/36519/4/src/mainboard/google/dralli... 
File src/mainboard/google/drallion/variants/drallion/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/36519/4/src/mainboard/google/dralli... 
PS4, Line 41: 	register "PchUsb2PhySusPgEnable" = "1"
> drallion has this issue as well. Need client to decide need this or not.

Ack