[coreboot-gerrit] [M] Change in coreboot[master]: drivers/intel/fsp2_0: Update MRC cache in ramstage

[Reka Norman (Code Review)]

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov.

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )

Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67669/comment/100e472e_4ff74ea9 
PS1, Line 18:
> Or what about that existing romstage_handoff CBMEM structure, what's that for, could we just add it in there?

Yeah, I found that too and considered adding it there. But it looks very generic, so I wasn't sure if we wanted to add platform-specific stuff to it.