Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26819
Change subject: soc/intel/cannonlake: Make use of SkipMpInit for MP Init ......................................................................
soc/intel/cannonlake: Make use of SkipMpInit for MP Init
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init
Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb M src/mainboard/google/zoombini/variants/meowth/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h 6 files changed, 7 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/26819/1
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 512354e..6f70dfb 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@
# FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 4076ea6..7d89b78 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -29,7 +29,6 @@
# FSP configuration register "SaGv" = "SaGv_Enabled" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 18aa65d..d5d806c 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -6,7 +6,6 @@
# FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 8bcb850..4c62800 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -6,7 +6,6 @@
# FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0c4232c..924764a 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -295,7 +295,7 @@
params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; - params->SkipMpInit = config->FspSkipMpInit; + params->SkipMpInit = !config->use_fsp_mp_init;
/* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 8fdb964..d943f9c 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -206,7 +206,12 @@ CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ } chipset_lockdown;
- uint8_t FspSkipMpInit; + /* + * Option for mainboard to skip coreboot MP initialization + * 0 = Make use of coreboot MP Init + * 1 = Make use of FSP MP Init + */ + uint8_t use_fsp_mp_init; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */