[coreboot-gerrit] Change in coreboot[master]: [TESTME] nb/intel/x4x: Correct DDR3 turnaround table

[Michael Büchler (Code Review)]

Attention is currently required from: Nico Huber, Damien Zammit, Angel Pons, Arthur Heymans, Patrick Rudolph.
Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49388 )

Change subject: [TESTME] nb/intel/x4x: Correct DDR3 turnaround table
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Patch Set 1: Code-Review+1

(1 comment)

Patchset:

PS1: 
I tested this with RAM sticks specified for DDR3-1066 with CAS latency (tCL) 7. Coreboot was tricked into using CL = 8 instead, as suggested on IRC. Without this change boot fails. With this change everything works including suspend/resume.