Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4851
-gerrit
commit 37c9fbfcf8d1cd79d174484549f42bd436bc2454 Author: Aaron Durbin adurbin@chromium.org Date: Tue Sep 24 12:29:57 2013 -0500
baytrail: add common pci_operations
The coreboot device modeling for pci devices wants a pci_operations structure for all devices. This structure just sets the subsystem vendor and device id. Add a common one that all the other pci drivers can use for Bay Trail.
BUG=chrome-os-partner:22860 BRANCH=None TEST=Built and booted while utilizing this new structure.
Change-Id: I39949cbdb83b3acb93fe4034eb4278d45369e321 Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://chromium-review.googlesource.com/170428 --- src/soc/intel/baytrail/baytrail/ramstage.h | 27 +++++++++++++++++++++++++++ src/soc/intel/baytrail/chip.c | 17 ++++++++++++++++- 2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h new file mode 100644 index 0000000..61fe9c3 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_RAMSTAGE_H_ +#define _BAYTRAIL_RAMSTAGE_H_ + +#include <device/device.h> + +extern struct pci_operations soc_pci_ops; + +#endif /* _BAYTRAIL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 5a5c364..09c36df 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -52,7 +52,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, .init = cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, };
@@ -72,3 +72,18 @@ struct chip_operations soc_intel_baytrail_ops = { CHIP_NAME("Intel BayTrail SoC") .enable_dev = enable_dev, }; + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +struct pci_operations soc_pci_ops = { + .set_subsystem = &pci_set_subsystem, +};