Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30608
Change subject: [WIP]drivers/cavium: Add UART PCI driver ......................................................................
[WIP]drivers/cavium: Add UART PCI driver
Move PCI handling from cn81xx/soc to its own pci driver.
Change-Id: I0fa2f086aba9b4f9c6dba7a35a84ea61c5fa64e4 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- A src/drivers/cavium/pci-cn8xxx/Kconfig A src/drivers/cavium/pci-cn8xxx/Makefile.inc A src/drivers/cavium/pci-cn8xxx/uart.c M src/include/device/pci_ids.h M src/soc/cavium/cn81xx/soc.c 5 files changed, 57 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30608/1
diff --git a/src/drivers/cavium/pci-cn8xxx/Kconfig b/src/drivers/cavium/pci-cn8xxx/Kconfig new file mode 100644 index 0000000..1de774f --- /dev/null +++ b/src/drivers/cavium/pci-cn8xxx/Kconfig @@ -0,0 +1,7 @@ +config DRIVERS_CAVIUM + bool + depends on SOC_CAVIUM_COMMON + default y if SOC_CAVIUM_COMMON + default n + help + When enabled, adds PCI drivers for Cavium SoCs. diff --git a/src/drivers/cavium/pci-cn8xxx/Makefile.inc b/src/drivers/cavium/pci-cn8xxx/Makefile.inc new file mode 100644 index 0000000..d85fc3e --- /dev/null +++ b/src/drivers/cavium/pci-cn8xxx/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_CAVIUM) += uart.c diff --git a/src/drivers/cavium/pci-cn8xxx/uart.c b/src/drivers/cavium/pci-cn8xxx/uart.c new file mode 100644 index 0000000..2230d5d --- /dev/null +++ b/src/drivers/cavium/pci-cn8xxx/uart.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <device/device.h> +#include <console/console.h> +#include <soc/uart.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void cavium_uart_init(struct device *dev) +{ + printk(BIOS_ERR, "UART: debug\n"); + + /* using device enable state from devicetree.cb */ + if (dev->enabled) { + const u8 fn = PCI_FUNC(dev->path.pci.devfn); + + /* Calling uart_setup with no baudrate will do minimal HW + * enough for the kernel to not panic */ + if (!uart_is_enabled(fn)) + uart_setup(fn, 0); + } +} + +static struct device_operations device_ops = { + .init = cavium_uart_init, +}; + +static const struct pci_driver soc_cavium_uart __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_CAVIUM, + .device = PCI_DEVICE_ID_CAVIUM_THUNDERX_UART, +}; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 751cca0..ba55f1d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -132,6 +132,9 @@ #define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 #define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8
+#define PCI_VENDOR_CAVIUM 0x177d +#define PCI_DEVICE_ID_CAVIUM_THUNDERX_UART 0xa00f + #define PCI_VENDOR_ID_COMPAQ 0x0e11 #define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 #define PCI_DEVICE_ID_COMPAQ_1280 0x3033 diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 2046d21..0748096 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -388,18 +388,6 @@ } }
- /* Init UARTs */ - size_t i; - struct device *uart_dev; - for (i = 0; i <= 3; i++) { - uart_dev = dev_find_slot(1, PCI_DEVFN(8, i)); - /* using device enable state from devicetree.cb */ - if (uart_dev && uart_dev->enabled) { - if (!uart_is_enabled(i)) - uart_setup(i, 0); - } - } - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) soc_init_atf(); }