Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15009
-gerrit
commit d5b5428ef15c0cc57ff670494675cdf0b4506318 Author: Lee Leahy leroy.p.leahy@intel.com Date: Mon May 30 14:35:15 2016 -0700
soc/intel/quark: Move UART init into romstage.c
Move UART initialization into romstage.c and eliminate uart.c.
TEST=Build and run on Galileo Gen2
Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/include/soc/pci_devs.h | 1 + src/soc/intel/quark/romstage/Makefile.inc | 1 - src/soc/intel/quark/romstage/romstage.c | 10 +++++-- src/soc/intel/quark/romstage/uart.c | 42 ------------------------------ 4 files changed, 9 insertions(+), 45 deletions(-)
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index ff9d65f..278a012 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -38,6 +38,7 @@ #define EHCI_FUNC 3 #define OHCI_FUNC 4 #define HSUART1_FUNC 5 +#define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC)
/* IO Fabric 2 */ #define SIO2_DEV 0x15 diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 2f29b06..6c92ac4 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -20,4 +20,3 @@ romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c -romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c86c2ea..5be022a 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -58,11 +58,17 @@ static const struct reg_script i2c_gpio_controller_init[] = { REG_SCRIPT_END };
+static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + void car_soc_pre_console_init(void) { if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, - UART_BASE_ADDRESS); + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); }
void car_soc_post_console_init(void) diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c deleted file mode 100644 index 9e8f6c5..0000000 --- a/src/soc/intel/quark/romstage/uart.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <device/pci.h> -#include <device/pci_def.h> -#include <rules.h> -#include <soc/romstage.h> - -int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) -{ - uint16_t reg16; - - /* HSUART controller #1 (B0:D20:F5). */ - pci_devfn_t uart_bdf = PCI_DEV(bus, dev, func); - - /* Decode BAR0(offset 0x10). */ - pci_write_config32(uart_bdf, PCI_BASE_ADDRESS_0, mmio_base); - - /* Enable MEMBASE at CMD(offset 0x04). */ - reg16 = pci_read_config16(uart_bdf, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(uart_bdf, PCI_COMMAND, reg16); - - return 0; -}