Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28957
Change subject: src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)" ......................................................................
src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)"
Change-Id: I7e340d42cc9498740fa7158f76472e26b5509695 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/google/stout/chromeos.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/packardbell/ms2290/smihandler.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/sapphire/pureplatinumh61/romstage.c 24 files changed, 200 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28957/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ee322ae..3d76f56 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -33,10 +33,12 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
/* I/O Decode Ranges * X60: 0x0210 == 00000010 00010000 @@ -46,7 +48,7 @@ * 00 = 378h - 37Fh and 778h - 77Fh * 10 = 3BCh - 3BEh and 7BCh - 7BEh */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
/* LPC_EN--LPC I/F Enables Register * X60: 0x1f0d == 00011111 00001101 @@ -100,7 +102,7 @@ * interface. This range is selected in the LPC_COM Decode * Range Register (D31:F0:80h, bits 3:2). */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
@@ -126,19 +128,19 @@ * 1 = Enable the GEN1 I/O range to be forwarded to the LPC * I/F */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0681);
/* GEN2_DEC, LPC Interface Generic Decode Range 2 * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c1641);
/* GEN4_DEC, LPC Interface Generic Decode Range 4 * X60: 0x0000 0x0000 * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301); + pci_write_config32(LPC_DEV, GEN4_DEC, 0x001c0301); }
static void rcba_config(void) @@ -188,14 +190,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
/* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
/* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index d189ae2..51fcb55 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -23,15 +23,17 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <cbfs.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); + pci_write_config16(LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(LPC_DEV, 0x80, 0x0070); + pci_write_config32(LPC_DEV, 0xac, 0x80000000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 90df5390..7c75bba 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -77,11 +77,11 @@
static void ich7_enable_lpc(void) { - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0291); }
void mainboard_romstage_entry(unsigned long bist) diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index dacc396..783df6b 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -39,6 +39,7 @@ #include <cpu/intel/speedstep.h> #include <arch/cpu.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
@@ -105,15 +106,15 @@ static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00040291); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00040291); }
static void rcba_config(void) @@ -138,14 +139,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index 3f81e67..871a331 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -36,6 +36,7 @@ #include <romstage_handoff.h> #include <timestamp.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)
/* Early mainboard specific GPIO setup */ @@ -56,16 +57,16 @@ static void nm10_enable_lpc(void) { /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + pci_write_config16(LPC_DEV, LPC_IO_DEC, + pci_read_config16(LPC_DEV, LPC_IO_DEC) | 0x0010); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
/* Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); }
static void rcba_config(void) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 7498247..71f2df1 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -33,6 +33,8 @@ #include <timestamp.h> #include "option_table.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void setup_special_ich7_gpios(void) { u32 gpios; @@ -60,19 +62,19 @@ lpt_en = LPT_LPC_EN;
// Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN); // Enable 0x02e0 - 0x2ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x001c02e1); // Enable 0x600 - 0x6ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x00fc0601); // Enable 0x68 - 0x6f - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x00040069); }
/* This box has two superios, so enabling serial becomes slightly excessive. @@ -192,14 +194,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 49a25af..4790e9e 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -34,6 +34,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) @@ -66,17 +67,17 @@ static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0000); // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0801); /* LPC decode range 2: Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x00040291); }
static void rcba_config(void) @@ -100,14 +101,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 13c888e..997c74b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -32,6 +32,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <timestamp.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) @@ -118,14 +119,14 @@ static void ich7_enable_lpc(void) { /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x007c0291); }
void mainboard_romstage_entry(unsigned long bist) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 6d77a2a..d9e9b59 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -26,6 +26,8 @@ #include "ec.h" #include <ec/quanta/it8518/ec.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h>
@@ -97,7 +99,7 @@ int get_recovery_mode_switch(void) { #ifdef __PRE_RAM__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = LPC_DEV; #else static int ec_in_rec_mode = 0; static int ec_rec_flag_good = 0; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 78ec5ed..84dc356 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -31,23 +31,24 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0)
static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); // Enable HWM at 0x290 - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0291); // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); + pci_write_config32(LPC_DEV, GEN4_DEC, 0x00000301); }
/* This box has one superio @@ -155,14 +156,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 77384ee..00c5cb8 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -35,6 +35,7 @@ #include <romstage_handoff.h> #include <timestamp.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0)
@@ -57,15 +58,15 @@ static void nm10_enable_lpc(void) { /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_IO_DEC, + pci_read_config16(LPC_DEV, LPC_IO_DEC) | 0x0010); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x7c0291); }
static void rcba_config(void) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 57f32c2..9f09391 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -29,20 +29,21 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c0681); }
static void rcba_config(void) @@ -80,14 +81,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index c4be4d50..5c18135 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -33,12 +33,14 @@ #define DEBUG_UART_EN COMA_LPC_EN #endif
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | DEBUG_UART_EN); /* Decode SuperIO 0x0a00 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x00fc0a01); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 467606a..6b0ec5b 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -33,6 +33,7 @@
#include "option_table.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
static void ich7_enable_lpc(void) @@ -42,21 +43,21 @@ lpt_en = LPT_LPC_EN; /* enable LPT */
/* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* Set COM1/COM2 decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable COM1/COM2/KBD/SuperIO1+2 */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN | COMB_LPC_EN | lpt_en); /* Enable HWM at 0xa00 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); /* COM3 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000403e9); /* COM4 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x000402e9); /* io 0x300 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); + pci_write_config32(LPC_DEV, GEN4_DEC, 0x00000301); }
/* This box has two superios, so enabling serial becomes slightly excessive. @@ -245,14 +246,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
/* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
/* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 0f6ffed..cd0bb08 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -23,13 +23,15 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(LPC_DEV, 0x82, 0x3c0c); + pci_write_config32(LPC_DEV, 0x84, 0x007c1611); + pci_write_config32(LPC_DEV, 0x88, 0x00040069); + pci_write_config32(LPC_DEV, 0x8c, 0x000c0701); + pci_write_config32(LPC_DEV, 0x90, 0x00000000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 7e002d4..0e6df78 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -28,22 +28,23 @@ #include <southbridge/intel/common/gpio.h> #include "ec.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SPD_LEN 256
void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); + pci_write_config16(LPC_DEV, 0x82, 0x0c00); + pci_write_config32(LPC_DEV, 0x84, 0x00000000); + pci_write_config32(LPC_DEV, 0x88, 0x000c0701); + pci_write_config32(LPC_DEV, 0x8c, 0x000c0069); + pci_write_config32(LPC_DEV, 0x90, 0x000c06a1); + pci_write_config32(LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */ pci_write_config32( - PCI_DEV(0, 0x1f, 0), 0x98, + LPC_DEV, 0x98, CONFIG_EC_BASE_ADDRESS | 1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0); + pci_write_config16(LPC_DEV, 0xd8, 0xffc0);
/* Enable external USB port power. */ if (IS_ENABLED(CONFIG_USBDEBUG)) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index e4a8efb..a52ea6d 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -36,25 +36,27 @@ #include <southbridge/intel/common/gpio.h> #include "dock.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
/* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601);
/* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1);
/* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681); }
static void early_superio_config(void) @@ -120,14 +122,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); @@ -181,9 +183,9 @@ ich7_enable_lpc();
/* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + pci_write_config8(LPC_DEV, 0x4c /* GC */, 0x10); setup_pch_gpios(&mainboard_gpio_map);
dock_err = dlpc_init(); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index d241422..66dee90 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -43,6 +43,8 @@ #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/me.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void pch_enable_lpc(void) { /* X201 EC Decode Range Port60/64, Port62/66 */ @@ -215,7 +217,7 @@ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(LPC_DEV, 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 81ee5da..9b86b4f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -36,24 +36,26 @@ #include <southbridge/intel/common/gpio.h> #include "dock.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601);
/* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1);
/* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681); }
static void early_superio_config(void) @@ -119,14 +121,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); @@ -177,8 +179,8 @@ enable_lapic();
/* Enable GPIOs */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */ + pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(LPC_DEV, 0x4c, 0x10); /* 0x4c == GC */ setup_pch_gpios(&mainboard_gpio_map);
ich7_enable_lpc(); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 94c8a8f..59afc7f 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -36,25 +36,27 @@ #include <southbridge/intel/common/gpio.h> #include "dock.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
/* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601);
/* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1);
/* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681); }
static void early_superio_config(void) @@ -120,14 +122,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); @@ -181,9 +183,9 @@ ich7_enable_lpc();
/* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + pci_write_config8(LPC_DEV, 0x4c /* GC */, 0x10); setup_pch_gpios(&mainboard_gpio_map);
dock_err = dlpc_init(); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index adb0cec..2507c8b 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -41,6 +41,8 @@ #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/me.h>
+#define LPC_DEV LPC_DEV + static void pch_enable_lpc(void) { /* Enable EC, PS/2 Keyboard/Mouse */ @@ -214,7 +216,7 @@ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(LPC_DEV, 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index 926650a..7b3e9d6 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -24,6 +24,8 @@ #include <ec/acpi/ec.h> #include <delay.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void mainboard_smm_init(void) { printk(BIOS_DEBUG, "initializing SMI\n"); @@ -74,16 +76,16 @@ mainboard_finalized = 1; break; case APM_CNT_ACPI_ENABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp = pci_read_config8(LPC_DEV, 0xbb); tmp &= ~0x03; tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + pci_write_config8(LPC_DEV, 0xbb, tmp); break; case APM_CNT_ACPI_DISABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp = pci_read_config8(LPC_DEV, 0xbb); tmp &= ~0x03; tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + pci_write_config8(LPC_DEV, 0xbb, tmp); break; default: break; diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7f233e8..b921382 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -35,6 +35,8 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include "option_table.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { int lpt_en = 0; @@ -42,19 +44,19 @@ lpt_en = LPT_LPC_EN; /* enable LPT */
/* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0007); /* decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN); /* COM3 and COM4 decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x1c02e1); /* ??decode?? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x00fc0601); /* EC decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x00040069); }
/* This box has two superios, so enabling serial becomes slightly excessive. @@ -158,14 +160,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
/* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8);
/* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index da825a9..cdc5993 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -25,16 +25,17 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h>
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); + pci_write_config16(LPC_DEV, 0x82, 0x2400); + pci_write_config32(LPC_DEV, 0x84, 0x000c0291); + pci_write_config32(LPC_DEV, 0x88, 0x000c0a01); + pci_write_config32(LPC_DEV, 0x8c, 0x00000000); + pci_write_config32(LPC_DEV, 0x90, 0x00000000); + pci_write_config16(LPC_DEV, 0x80, 0x0000); + pci_write_config32(LPC_DEV, 0xac, 0x00010000); }
void mainboard_rcba_config(void)