Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Subrata Banik, Wonkyu Kim.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80088?usp=email )
Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB ......................................................................
Patch Set 6: Code-Review-1
(3 comments)
Patchset:
PS5:
This patch is for access upto 512GB only and verified on 64bit mode with 38-bit and 42-bit hardware. Are you using any different mode?
It was on a 36-bit physical address cpu, but it has been some time so my memory could be false.
I used the following.
/* SPDX-License-Identifier: GPL-2.0-only */
/* * For reference see "AMD64 Architecture Programmer's Manual Volume 2", * Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4 * * Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty */
.section .rodata #define _PRES (1ULL << 0) #define _RW (1ULL << 1) #define _US (1ULL << 2) #define _A (1ULL << 5) #define _D (1ULL << 6) #define _PS (1ULL << 7) #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
.global PM4LE .align 32 PM4LE: .quad _GEN_DIR(PDPE_table)
.align 4096 PDPE_table: /* identity map 1G pages */ .rept 32 .quad _GEN_PAGE(0x40000000 * ((. - PDPE_table) >> 3)) .endr
File src/cpu/x86/64bit/pt1G.S:
https://review.coreboot.org/c/coreboot/+/80088/comment/ebea3bc3_e6b844d5 : PS6, Line 19: PM align to 32
https://review.coreboot.org/c/coreboot/+/80088/comment/fed948cc_acbc837f : PS6, Line 23: 16 needs to align to 4096