Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3811
-gerrit
commit b2e4581a03e2413fcf6231ceefb82274650b2ff9 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Jul 26 08:52:10 2013 +0300
intel/i945 intel/i82801gx: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO.
Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/northbridge/intel/i945/early_init.c | 140 ++++++++++++++-------------- src/southbridge/intel/i82801gx/azalia.c | 24 ++--- src/southbridge/intel/i82801gx/i82801gx.c | 4 + src/southbridge/intel/i82801gx/pcie.c | 13 +-- src/southbridge/intel/i82801gx/smihandler.c | 10 +- 5 files changed, 94 insertions(+), 97 deletions(-)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 946f7aa..57232af 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -529,9 +529,9 @@ static void i945_setup_pci_express_x16(void) reg16 |= DEVEN_D1F0; pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x208); reg32 &= ~(1 << 8); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32);
/* We have no success with querying the usual PCIe registers * for link setup success on the i945. Hence we assign a temporary @@ -560,33 +560,33 @@ static void i945_setup_pci_express_x16(void) pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a); pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 &= ~(1 << 8); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
/* Initialze PEG_CAP */ - reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); reg16 |= (1 << 8); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16);
/* Setup SLOTCAP */ /* TODO: These values are mainboard dependent and should * be set from devicetree.cb. */ /* NOTE: SLOTCAP becomes RO after the first write! */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); reg32 &= 0x0007ffff;
reg32 &= 0xfffe007f;
- pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
/* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -597,21 +597,21 @@ static void i945_setup_pci_express_x16(void)
printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); reg32 &= ~(0xf << 1); reg32 |=1; - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32);
- reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
reg16 |= (1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); reg16 &= ~(1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -624,22 +624,22 @@ static void i945_setup_pci_express_x16(void) } }
- reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); reg16 >>= 4; reg16 &= 0x3f; /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204); reg32 &= 0xfffffc00; /* clear [9:0] */ if (reg16 == 1) { reg32 |= 0x32b; // TODO - /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ + /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ } else if (reg16 == 16) { reg32 |= 0x0f4; // TODO - /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ + /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ }
reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); @@ -661,82 +661,82 @@ static void i945_setup_pci_express_x16(void) }
/* Enable GPEs */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
/* Virtual Channel Configuration: Only VC0 on PCIe x16 */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x114); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114); reg32 &= 0xffffff01; - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
/* Extended VC count */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x104); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104); reg32 &= ~(7 << 0); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32);
/* Active State Power Management ASPM */
/* TODO */
/* Clear error bits */ - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff);
/* Program R/WO registers */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x308); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x314); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x324); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x328); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32);
- reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); - pcie_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); + pci_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8);
/* Additional PCIe graphics setup */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 24); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (1 << 5); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x200); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200); reg32 &= ~(3 << 26); reg32 |= (2 << 26); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); if (i945_silicon_revision() >= 2) { reg32 |= (1 << 12); } else { reg32 &= ~(1 << 12); } - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); reg32 &= ~(1 << 31); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); reg32 |= (1 << 31); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32);
if (i945_silicon_revision() >= 3) { static const u32 reglist[] = { @@ -747,21 +747,21 @@ static void i945_setup_pci_express_x16(void)
int i; for (i=0; i<ARRAY_SIZE(reglist); i++) { - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); reg32 &= 0x0fffffff; reg32 |= (2 << 28); - pcie_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); } }
if (i945_silicon_revision() <= 2 ) { /* Set voltage specific parameters */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); reg32 &= (0xf << 4); /* Default case 1.05V */ if ((MCHBAR32(0xe08) & (1 << 20)) == 0) { /* 1.50V */ reg32 |= (7 << 4); } - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); }
return; @@ -772,21 +772,21 @@ disable_pciexpress_x16_link:
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
- reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 |= (1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
- reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 |= (1 << 8); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
- reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 &= ~(1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; - for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); + for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); (reg32 & 0x000f0000) && --timeout;) ; if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); @@ -836,10 +836,10 @@ static void i945_setup_root_complex_topology(void)
/* PCI Express x16 Port Root Topology */ if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x150); reg32 |= (1 << 0); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); } }
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 26859c5..cb1a37d 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -224,39 +224,35 @@ static void azalia_init(struct device *dev) u8 reg8; u32 reg32;
-#if CONFIG_MMCONF_SUPPORT // ESD - reg32 = pci_mmio_read_config32(dev, 0x134); + reg32 = pci_read_config32(dev, 0x134); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x134, reg32); + pci_write_config32(dev, 0x134, reg32);
// Link1 description - reg32 = pci_mmio_read_config32(dev, 0x140); + reg32 = pci_read_config32(dev, 0x140); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x140, reg32); + pci_write_config32(dev, 0x140, reg32);
// Port VC0 Resource Control Register - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32);
// VCi traffic class - reg8 = pci_mmio_read_config8(dev, 0x44); + reg8 = pci_read_config8(dev, 0x44); reg8 |= (7 << 0); // TC7 - pci_mmio_write_config8(dev, 0x44, reg8); + pci_write_config8(dev, 0x44, reg8);
// VCi Resource Control - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map - pci_mmio_write_config32(dev, 0x120, reg32); -#else -#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT -#endif + pci_write_config32(dev, 0x120, reg32);
/* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 7fe14bd..ed5921b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -23,6 +23,10 @@ #include <device/pci.h> #include "i82801gx.h"
+#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT +#endif + void i82801gx_enable(device_t dev) { u32 reg32; diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 1bc1bed..0825dec 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -55,20 +55,17 @@ static void pci_init(struct device *dev) reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); pci_write_config32(dev, 0xe1, reg32);
-#if CONFIG_MMCONF_SUPPORT /* Set VC0 transaction class */ - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32);
/* Mask completion timeouts */ - reg32 = pci_mmio_read_config32(dev, 0x148); + reg32 = pci_read_config32(dev, 0x148); reg32 |= (1 << 14); - pci_mmio_write_config32(dev, 0x148, reg32); -#else -#error "MMIO needed for ICH7 PCIe" -#endif + pci_write_config32(dev, 0x148, reg32); + /* Enable common clock configuration */ // Are there cases when we don't want that? reg16 = pci_read_config16(dev, 0x50); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 03c5d09..ba4d014 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -319,13 +319,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) { reg8 &= ~1; } else { reg8 |= 1; } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -494,7 +494,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -508,7 +508,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -635,7 +635,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts;
/* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's * happening in the following calls.