Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69925 )
Change subject: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size ......................................................................
mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size
Add RAM ID=3 define to 8GB size same as RAM ID 1.
BUG=b:259301885 BRANCH=Octopus TEST=Verified on Phaser
Signed-off-by: Stanley Wu stanley1.wu@lcfc.corp-partner.google.com Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 --- M src/mainboard/google/octopus/variants/phaser/Makefile.inc A src/mainboard/google/octopus/variants/phaser/memory.c 2 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/69925/1
diff --git a/src/mainboard/google/octopus/variants/phaser/Makefile.inc b/src/mainboard/google/octopus/variants/phaser/Makefile.inc index 37270eb..22ef41c 100644 --- a/src/mainboard/google/octopus/variants/phaser/Makefile.inc +++ b/src/mainboard/google/octopus/variants/phaser/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += gpio.c
+romstage-y += memory.c + ramstage-y += variant.c ramstage-y += gpio.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/phaser/memory.c b/src/mainboard/google/octopus/variants/phaser/memory.c new file mode 100644 index 0000000..04c314f --- /dev/null +++ b/src/mainboard/google/octopus/variants/phaser/memory.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <variant/gpio.h> + +size_t variant_memory_sku(void) +{ + size_t rt; + gpio_t pads[] = { + [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, + }; + + rt = gpio_base2_value(pads, ARRAY_SIZE(pads)); + return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1 +} \ No newline at end of file