Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40398 )
Change subject: [wip] Enable USB3 DBC ......................................................................
[wip] Enable USB3 DBC
Signed-off-by: Kane Chen kane.chen@intel.com Change-Id: Iec87e31f3eae9e382e059c3288066802863cf0ad --- M 3rdparty/blobs M 3rdparty/intel-microcode M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/40398/1
diff --git a/3rdparty/blobs b/3rdparty/blobs index 7ad2d22..b267c36 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 7ad2d22452225a14c19b17570cb77920d8fc81a5 +Subproject commit b267c3608629cd0d9807e1ccbbe32ce318823569 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 1dd14da..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 1dd14da6d1ea5cfbd95923653f31c04aac3aa655 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 9933200..3d64ed0 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -190,6 +190,8 @@
soc_memory_init_params(m_cfg, config); mainboard_memory_init_params(mupd); + m_cfg->PlatformDebugConsent = 3; + }
__weak void mainboard_memory_init_params(FSPM_UPD *mupd)