[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetree

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33739 )

Change subject: soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetree
......................................................................

soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetree

This patch sets required FSP UPDs to skip IGD initialziation if
devicetree has disable IGD.

Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33739
Reviewed-by: Furquan Shaikh 
Reviewed-by: Aamir Bohra 
Reviewed-by: Wonkyu Kim 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/icelake/romstage/fsp_params.c
2 files changed, 28 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Aamir Bohra: Looks good to me, approved
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index 03b00d9..382b184 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -80,9 +80,20 @@

mainboard_silicon_init_params(params);

-	params->PeiGraphicsPeimInit = 1;
-	params->GtFreqMax = 2;
-	params->CdClock = 3;
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
+
+	if (!dev || !dev->enabled) {
+		/*
+		 * Skip IGD initialization in FSP in case device is disabled
+		 * in the devicetree.cb.
+		 */
+		params->PeiGraphicsPeimInit = 0;
+	} else {
+		params->PeiGraphicsPeimInit = 1;
+		params->GtFreqMax = 2;
+		params->CdClock = 3;
+	}
+
    /* Unlock upper 8 bytes of RTC RAM */
    params->PchLockDownRtcMemoryLock = 0;

diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 4801bd9..89dc99a 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -25,11 +25,22 @@
    	const struct soc_intel_icelake_config *config)
 {
    unsigned int i;
-	const struct device *dev;
+	const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
    uint32_t mask = 0;

-	/* Set IGD stolen size to 60MB. */
-	m_cfg->IgdDvmt50PreAlloc = 0xFE;
+	if (!dev || !dev->enabled) {
+		/*
+		 * Skip IGD initialization in FSP if device
+		 * is disable in devicetree.cb.
+		 */
+		m_cfg->InternalGfx = 0;
+		m_cfg->IgdDvmt50PreAlloc = 0;
+	} else {
+		m_cfg->InternalGfx = 1;
+		/* Set IGD stolen size to 60MB. */
+		m_cfg->IgdDvmt50PreAlloc = 0xFE;
+	}
+
    m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
    m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
    m_cfg->SaGv = config->SaGv;