[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size

[Arthur Heymans (Code Review)]

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Himanshu Sahdev, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email )

Change subject: soc/amd/smm: Check the SMM TSEG size
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Patch Set 6: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/75405/comment/3ede4c4c_ac4524f9 :
PS3, Line 10: The SMM TSEG size should be less than SMM reserved size, bigger than
            : 8M, and power of 2.
> > I can not find the solid proof that it should be power of 2. […]

AMD TSEG mask works like an MTRR. It needs to be aligned to it's size and it's size needs to be a power of 2.

The reason it needs to have that 8M alignment on Intel is because TOLUD also has an 8M alignment, iirc. Intel TSEG+protection implementation differ from AMD and is often SOC/CPU specific. For AMD it can be considered architectural (same since amdk8 2003) and is indeed described in AMD64 architecture docs.