Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3267
-gerrit
commit fd332c67cfbbbe0fa15cf4835a1b2ba65890ea01 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Tue May 21 14:43:45 2013 -0500
dram: Add utilities for decoding DDR3 SPDs
Add convenience utilities for decoding DDR3 SPDs and printing the information to the console. These have proven invaluable when writing the VX900 memory initialization.
These are used in the VX900 branch
Information printed has the following format:
> SPD Data for DIMM 51 > Revision: 10 > Type : b > Key : 2 > Banks : 8 > Capacity: 1 Gb > Supported voltages: 1.5V > SDRAM width : 8 > Bus extension : 0 bits > Bus width : 64 > Optional features : DLL-Off_mode RZQ/7 RZQ/6 > Thermal features : ASR ext_temp_range > Thermal sensor : no > Standard SDRAM : no > Row addr bits : 13 > Column addr bits : 10 > Number of ranks : 1 > DIMM Capacity : 1024 MB > CAS latencies : 6 7 8 9 > tCKmin : 1.500 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 36.000 ns > tRCmin : 49.125 ns > tRFCmin : 110.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns
Change-Id: I30725a75caf74ac637db0a143344562bd9910466 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/device/dram/ddr3.c | 340 +++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr3.h | 158 +++++++++++++++++++ 2 files changed, 498 insertions(+)
diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c new file mode 100644 index 0000000..e7aae39 --- /dev/null +++ b/src/device/dram/ddr3.c @@ -0,0 +1,340 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2013 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/** + * @file ddr3_util.h + * + * \brief Utilities for decoding DDR3 SPDs + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/dram/ddr3.h> + +/** + * \brief Checks if the DIMM is Registered based on byte[3] of the SPD + * + * Tells if the DIMM type is registered or not. + * + * @param type DIMM type. This is byte[3] of the SPD. + */ +int dimm_is_registered(enum spd_dimm_type type) +{ + if ((type == SPD_DIMM_TYPE_RDIMM) + | (type == SPD_DIMM_TYPE_MINI_RDIMM) + | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + return 1; + + return 0; +} + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR3 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr stucture where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + */ +void spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) +{ + int nCRC, i; + u16 crc, spd_crc; + u8 *ptr = spd; + u8 ftb_divisor; + u8 ftb_dividend; + u8 capacity_shift, bus_width, sdram_width; + u32 mtb; /* medium time base */ + /* Don't assume we memset 0 dimm struct. Clear all our flags */ + dimm->flags.raw = 0; + /* Make sure that the SPD dump is indeed from a DDR3 module */ + if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) { + printram("Not a DDR3 SPD!\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return; + } + dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; + + /* Find the number of bytes covered by CRC */ + if (spd[0] & 0x80) { + nCRC = 117; + } else { + nCRC = 126; + } + + /* Compute the CRC */ + crc = 0; + while (--nCRC >= 0) { + crc = crc ^ (int)*ptr++ << 8; + for (i = 0; i < 8; ++i) + if (crc & 0x8000) { + crc = crc << 1 ^ 0x1021; + } else { + crc = crc << 1; + } + } + /* Compare with the CRC in the SPD */ + spd_crc = (spd[127] << 8) + spd[126]; + /* Verify the CRC is correct */ + if (crc != spd_crc) + printram("ERROR: SPD CRC failed!!!"); + + unsigned int reg, val, param; + printram(" Revision: %x\n", spd[1]); + printram(" Type : %x\n", spd[2]); + printram(" Key : %x\n", spd[3]); + + reg = spd[4]; + /* Number of memory banks */ + val = (reg >> 4) & 0x07; + if (val > 0x03) + printram(" Invalid number of memory banks\n"); + param = 1 << (val + 3); + printram(" Banks : %u\n", param); + /* SDRAM capacity */ + capacity_shift = reg & 0x0f; + if (capacity_shift > 0x06) + printram(" Invalid module capacity\n"); + if (capacity_shift < 0x02) { + printram(" Capacity: %u Mb\n", 256 << capacity_shift); + } else { + printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2)); + } + + reg = spd[5]; + /* Row address bits */ + val = (reg >> 4) & 0x07; + if (val > 0x04) + printram(" Invalid row address bits\n"); + dimm->row_bits = val + 12; + /* Column address bits */ + val = reg & 0x07; + if (val > 0x03) + printram(" Invalid column address bits\n"); + dimm->col_bits = val + 9; + + /* Module nominal voltage */ + reg = spd[6]; + printram(" Supported voltages:"); + if (reg & (1 << 2)) { + dimm->flags.operable_1_50V = 1; + printram(" 1.2V"); + } + if (reg & (1 << 1)) { + dimm->flags.operable_1_35V = 1; + printram(" 1.35V"); + } + if (!(reg & (1 << 0))) { + dimm->flags.operable_1_50V = 1; + printram(" 1.5V"); + } + printram("\n"); + + /* Module organization */ + reg = spd[7]; + /* Number of ranks */ + val = (reg >> 3) & 0x07; + if (val > 3) + printram(" Invalid number of ranks\n"); + dimm->ranks = val + 1; + /* SDRAM device width */ + val = (reg & 0x07); + if (val > 3) + printram(" Invalid SDRAM width\n"); + sdram_width = (4 << val); + printram(" SDRAM width : %u\n", sdram_width); + + /* Memory bus width */ + reg = spd[8]; + /* Bus extension */ + val = (reg >> 3) & 0x03; + if (val > 1) + printram(" Invalid bus extension\n"); + dimm->flags.is_ecc = val ? 1 : 0; + printram(" Bus extension : %u bits\n", val ? 8 : 0); + /* Bus width */ + val = reg & 0x07; + if (val > 3) + printram(" Invalid bus width\n"); + bus_width = 8 << val; + printram(" Bus width : %u\n", bus_width); + + /* We have all the info we need to compute the dimm size */ + /* Capacity is 256Mbit multiplied by the power of 2 specified in + * capacity_shift + * The rest is the JEDEC formula */ + /* I am certain it will fit in 16 bits + * Remember, It's in units of 2^24 bytes*/ + dimm->size = ((1 << (capacity_shift + (25 - 24))) * bus_width + * dimm->ranks) / sdram_width; + + /* Fine Timebase (FTB) Dividend/Divisor */ + /* Dividend */ + ftb_dividend = (spd[9] >> 4) & 0x0f; + /* Divisor */ + ftb_divisor = spd[9] & 0x0f; + + /* Medium Timebase = + * Medium Timebase (MTB) Dividend / + * Medium Timebase (MTB) Divisor */ + mtb = (((u32) spd[10]) << 8) / spd[11]; + + /* SDRAM Minimum Cycle Time (tCKmin) */ + dimm->tCK = spd[12] * mtb; + /* CAS Latencies Supported */ + dimm->cas_supported = (spd[15] << 8) + spd[14]; + /* Minimum CAS Latency Time (tAAmin) */ + dimm->tAA = spd[16] * mtb; + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd[17] * mtb; + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd[18] * mtb; + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd[19] * mtb; + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = spd[20] * mtb; + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb; + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb; + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd[26] * mtb; + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd[27] * mtb; + /* Minimum Four Activate Window Delay Time (tFAWmin) */ + dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; + + /* SDRAM Optional Features */ + reg = spd[30]; + printram(" Optional features :"); + if (reg & 0x80) { + dimm->flags.dll_off_mode = 1; + printram(" DLL-Off_mode"); + } + if (reg & 0x02) { + dimm->flags.rzq7_supported = 1; + printram(" RZQ/7"); + } + if (reg & 0x01) { + dimm->flags.rzq6_supported = 1; + printram(" RZQ/6"); + } + printram("\n"); + + /* SDRAM Thermal and Refresh Options */ + reg = spd[31]; + printram(" Thermal features :"); + if (reg & 0x80) { + dimm->flags.pasr = 1; + printram(" PASR"); + } + if (reg & 0x08) { + dimm->flags.odts = 1; + printram(" ODTS"); + } + if (reg & 0x04) { + dimm->flags.asr = 1; + printram(" ASR"); + } + if (reg & 0x02) { + dimm->flags.ext_temp_range = 1; + printram(" ext_temp_refresh"); + } + if (reg & 0x01) { + dimm->flags.ext_temp_refresh = 1; + printram(" ext_temp_range"); + } + printram("\n"); + + /* Module Thermal Sensor */ + reg = spd[32]; + if (reg & 0x80) + dimm->flags.therm_sensor = 1; + printram(" Thermal sensor : %s\n", + dimm->flags.therm_sensor ? "yes" : "no"); + + /* SDRAM Device Type */ + reg = spd[33]; + printram(" Standard SDRAM : %s\n", (reg & 0x80) ? "yes" : "no"); + + if (spd[60] & 0x01) { + dimm->flags.pins_mirrored = 1; + printram(" DIMM Rank1 Address bits mirrorred!!!\n"); + } + +} + +static void print_ns(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printram("%s%3u.%.3u ns\n", msg, mant, fp); +} + +/** +* \brief Print the info in dimm +* +* Print info about the dimm. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* selected. +* +* @param dimm pointer to already decoded @ref dimm_attr stucture +*/ +void dram_print_spd_ddr3(const dimm_attr * dimm) +{ + u16 val16; + int i; + + printram(" Row addr bits : %u\n", dimm->row_bits); + printram(" Column addr bits : %u\n", dimm->col_bits); + printram(" Number of ranks : %u\n", dimm->ranks); + printram(" DIMM Capacity : %u MB\n", dimm->size << 4); + + /* CAS Latencies Supported */ + val16 = dimm->cas_supported; + printram(" CAS latencies :"); + i = 0; + do { + if (val16 & 1) + printram(" %u", i + 4); + i++; + val16 >>= 1; + } while (val16); + printram("\n"); + + print_ns(" tCKmin : ", dimm->tCK); + print_ns(" tAAmin : ", dimm->tAA); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tFAWmin : ", dimm->tFAW); + +} diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h new file mode 100644 index 0000000..6770dd6 --- /dev/null +++ b/src/include/device/dram/ddr3.h @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef DEVICE_DRAM_DDR3L_H +#define DEVICE_DRAM_DDR3L_H + +/** + * @file ddr3.h + * + * \brief Utilities for decoding DDR3 SPDs + */ + +#include <stdint.h> +#include <spd.h> + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR3 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define TCK_1066MHZ 240 +#define TCK_800MHZ 320 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/** + * \brief DIMM flags + * + * Characteristic flags for the DIMM, as presented by the SPD + */ +typedef union dimm_flags_st { + /* The whole point of the union/struct construct is to allow us to clear + * all the bits with one line: flags.raw = 0. + * We do not care how these bits are ordered */ + struct { + /* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See: + * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */ + unsigned pins_mirrored:1; + /* Module can work at 1.50V - All DIMMS must be 1.5V operable */ + unsigned operable_1_50V:1; + /* Module can work at 1.35V */ + unsigned operable_1_35V:1; + /* Module can work at 1.20V */ + unsigned operable_1_20V:1; + /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ + unsigned is_ecc:1; + /* DLL-Off Mode Support */ + unsigned dll_off_mode:1; + /* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */ + unsigned rzq6_supported:1; + /* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */ + unsigned rzq7_supported:1; + /* Partial Array Self Refresh */ + unsigned pasr:1; + /* On-die Thermal Sensor Readout */ + unsigned odts:1; + /* Auto Self Refresh */ + unsigned asr:1; + /* Extended temperature range supported */ + unsigned ext_temp_range:1; + /* Operating at extended temperature requires 2X refresh rate */ + unsigned ext_temp_refresh:1; + /* Thermal sensor incorporated */ + unsigned therm_sensor:1; + }; + unsigned raw; +} dimm_flags_t; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + u16 cas_supported; + /* Flags extracted from SPD */ + dimm_flags_t flags; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Size of module in (1 << 24) bytes (16MB) */ + u16 size; + /* Latencies are in units of 1/256 ns */ + u32 tCK; + u32 tAA; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tFAW; +} dimm_attr; + +typedef u8 spd_raw_data[256]; + +void spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data); +int dimm_is_registered(enum spd_dimm_type type); +void dram_print_spd_ddr3(const dimm_attr * dimm); + +/** + * \brief Read double word from specified address + * + * Should be useful when doing an MRS to the DIMM + */ +static inline u32 volatile_read(volatile u32 addr) +{ + volatile u32 result; + result = *(volatile u32 *)addr; + return result; +} + +#endif /* DEVICE_DRAM_DDR3_H */