EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40487 )
Change subject: mb/google/deltaur: Update H1 I2C gpio pin setting ......................................................................
mb/google/deltaur: Update H1 I2C gpio pin setting
H1 using I2C3 in the HW schematics and connect to GPP_H6 and GPP_H7.
BUG=b:150165131
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36 --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c 1 file changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/40487/1
diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 46a5cdd..71a07b6 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -303,14 +303,14 @@ PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ PAD_CFG_GPI(GPP_H5, NONE, DEEP), - /* H6 : GPP_H6 ==> SPK_DET1 */ - PAD_CFG_GPI(GPP_H6, NONE, PLTRST), - /* H7 : GPP_H7 ==> NC */ - PAD_NC(GPP_H7, NONE), - /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : GPP_H8 ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : GPP_H9 ==> NC */ + PAD_NC(GPP_H9, NONE), /* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */ @@ -436,10 +436,10 @@ PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ PAD_CFG_GPI(GPP_H5, NONE, DEEP), - /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* GPD3: GPD3 ==> SIO_PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), };