Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45192 )
Change subject: soc/intel/alderlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 9: Code-Review+2
(2 comments)
LGTM.
https://review.coreboot.org/c/coreboot/+/45192/7/src/soc/intel/alderlake/mem... File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/45192/7/src/soc/intel/alderlake/mem... PS7, Line 109: uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */
yes, will fix it now
Thanks
https://review.coreboot.org/c/coreboot/+/45192/8/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/45192/8/src/soc/intel/alderlake/rom... PS8, Line 69: /* DP port config */ : m_cfg->DdiPortAConfig = config->DdiPortAConfig; : m_cfg->DdiPortBConfig = config->DdiPortBConfig; : m_cfg->DdiPortAHpd = config->DdiPortAHpd; : m_cfg->DdiPortBHpd = config->DdiPortBHpd; : m_cfg->DdiPortCHpd = config->DdiPortCHpd; : m_cfg->DdiPort1Hpd = config->DdiPort1Hpd; : m_cfg->DdiPort2Hpd = config->DdiPort2Hpd; : m_cfg->DdiPort3Hpd = config->DdiPort3Hpd; : m_cfg->DdiPort4Hpd = config->DdiPort4Hpd; : m_cfg->DdiPortADdc = config->DdiPortADdc; : m_cfg->DdiPortBDdc = config->DdiPortBDdc; : m_cfg->DdiPortCDdc = config->DdiPortCDdc; : m_cfg->DdiPort1Ddc = config->DdiPort1Ddc; : m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; : m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; : m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
you are right but the problem is FSP UPD default value, unless we override those, it might again ove […]
Welp. I think we can keep it like this for now.
If we wanted to avoid this kind of stuff, we could read the GPIO state as programmed by coreboot and write it here, but that would make it necessary to program the relevant GPIOs in romstage. Either way, it's not ideal...