[coreboot-gerrit] Change in coreboot[master]: inteltool: add Lewisburg C62x GPIOs support

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34942 )

Change subject: inteltool: add Lewisburg C62x GPIOs support
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Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34942/7/util/inteltool/pcr.c 
File util/inteltool/pcr.c:

PS7:
> Fixed. […]

I guess the Super SKU is an unfused chip, with all the silicon features enabled.

Making a single configurable chip design is cheaper than mamking ten specific chip designs, and also allows for downbinning parts with a few issues, e.g.: SATA ports 4 and 5 on a SunrisePoint desktop PCH are unstable? disable them, and bin it as an H110 PCH.

To disable these things, I guess Intel just blows a few fuses to obtain the desired configuration. Of course, healthy blocks might be disabled on some chips to meet volume requirements.

Several years ago, AMD did that with cores on CPUs and GPUs, but apparently the disablement wasn't permanent. People would cross-flash GPUs to higher models and hope the extra cores would be functional, and mainboards had options to try enabling the extra CPU cores. I don't think AMD liked that much :D