Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56853 )
Change subject: mb/*/brya/adlrvp: move device cpu_cluster to soc/chipset.cb ......................................................................
mb/*/brya/adlrvp: move device cpu_cluster to soc/chipset.cb
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC.
BUG=None BRANCH=None TEST=Change has no functional impact on the brya board.
Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964 Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/soc/intel/alderlake/chipset.cb 5 files changed, 2 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56853/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 1627961..eb85cb5 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake
- device cpu_cluster 0 on end - # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_E" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 3591a7b..8a779bc 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake
- device cpu_cluster 0 on end - register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
# GPE configuration diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index f4852b9..d4a2eb7 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake
- device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 3669c86..b28f387 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -6,8 +6,6 @@ end chip soc/intel/alderlake
- device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 532ec38..2d5c54e 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -1,5 +1,7 @@ chip soc/intel/alderlake
+ device cpu_cluster 0 on end + register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55,