Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85740?usp=email )
Change subject: soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE ......................................................................
soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE
The MFGPLL_*_BASE addresses are based on MFGSYS_BASE (0x40000000) instead of IO_PHYS (0x10000000). Rewrite the address calculation for readability.
Change-Id: Ifd5d77b95c698cb6030c58ba259f2cdf2a29d87b Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/soc/mediatek/mt8196/include/soc/addressmap.h 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85740/1
diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 96efa40..15a2e38 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -191,9 +191,9 @@ OVLSYS1_CONFIG_BASE = IO_PHYS + 0x22C00000, DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x2E800000, EDP_BASE = IO_PHYS + 0x2EC40000, - MFGPLL_PLL_CTRL_BASE = IO_PHYS + 0x3B810000, - MFGPLL_SC0_PLL_CTRL_BASE = IO_PHYS + 0x3B810400, - MFGPLL_SC1_PLL_CTRL_BASE = IO_PHYS + 0x3B810800, + MFGPLL_PLL_CTRL_BASE = MFGSYS_BASE + 0x0B810000, + MFGPLL_SC0_PLL_CTRL_BASE = MFGSYS_BASE + 0x0B810400, + MFGPLL_SC1_PLL_CTRL_BASE = MFGSYS_BASE + 0x0B810800, };
#endif