Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62095 )
Change subject: nb/amd/amdfam10/bootblock.c: Use generic PCI find capability functions ......................................................................
nb/amd/amdfam10/bootblock.c: Use generic PCI find capability functions
Use generic PCI capability functions and reduce the indentation level by 1.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ie35c3c3b951df2ce3c6e459a6e94d03a4720179d --- M src/northbridge/amd/amdfam10/bootblock.c 1 file changed, 69 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/62095/1
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 07f3d6b..f595b70 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -71,102 +71,89 @@ next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { u32 id; - u8 hdr_type, pos; + u8 pos; last_unitid = next_unitid;
id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID); /* If the chain is enumerated quit */ if (id == 0 || id == ULONG_MAX) - { break; - }
- hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE); - pos = 0; - hdr_type &= 0x7f; + pos = pci_s_find_capability(PCI_DEV(0,0,0), PCI_CAP_ID_HT);
- if ((hdr_type == PCI_HEADER_TYPE_NORMAL) || - (hdr_type == PCI_HEADER_TYPE_BRIDGE)) - { - pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST); - } while (pos != 0) { - u8 cap; - cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID); - if (cap == PCI_CAP_ID_HT) { - u16 flags; - /* - * Read and write and reread flags so the link - * direction bit is valid. - */ - flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); - pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); - flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); - if ((flags >> 13) == 0) { - unsigned int count; - unsigned int ctrl, ctrl_off; - pci_devfn_t devx; + u16 flags; + /* + * Read and write and reread flags so the link + * direction bit is valid. + */ + flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); + pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); + flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); + if ((flags >> 13) == 0) { + unsigned int count; + unsigned int ctrl, ctrl_off; + pci_devfn_t devx;
- if (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20) { - if (next_unitid >= 0x18) { - if (!end_used) { - next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; - end_used = 1; - } else { - goto out; - } - } - real_last_unitid = next_unitid; - real_last_pos = pos; - ht_dev_num++; - } - - if (CONFIG_HT_CHAIN_END_UNITID_BASE == 0) { - if (!next_unitid) - goto out; - } - - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - devx = PCI_DEV(0, next_unitid, 0); - next_unitid += count; - - pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); - - /* Test for end of chain */ - ctrl_off = ((flags >> 10) & 1)? - PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; - - do { - ctrl = pci_read_config16(devx, pos + ctrl_off); - /* Is this the end of the hypertransport chain? */ - if (ctrl & (1 << 6)) { + if (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20) { + if (next_unitid >= 0x18) { + if (!end_used) { + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; + end_used = 1; + } else { goto out; } - - if (ctrl & ((1 << 4) | (1 << 8))) { - /* - * Either the link has failed, or we have - * a CRC error. - * Sometimes this can happen due to link - * retrain, so lets knock it down and see - * if its transient - */ - ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc - pci_write_config16(devx, pos + ctrl_off, ctrl); - ctrl = pci_read_config16(devx, pos + ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - /* Can not clear the error */ - break; - } - } - } while ((ctrl & (1 << 5)) == 0); - - break; + } + real_last_unitid = next_unitid; + real_last_pos = pos; + ht_dev_num++; } + + if (CONFIG_HT_CHAIN_END_UNITID_BASE == 0) { + if (!next_unitid) + goto out; + } + + flags &= ~0x1f; + flags |= next_unitid & 0x1f; + count = (flags >> 5) & 0x1f; + devx = PCI_DEV(0, next_unitid, 0); + next_unitid += count; + + pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); + + /* Test for end of chain */ + ctrl_off = ((flags >> 10) & 1)? + PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; + + do { + ctrl = pci_read_config16(devx, pos + ctrl_off); + /* Is this the end of the hypertransport chain? */ + if (ctrl & (1 << 6)) { + goto out; + } + + if (ctrl & ((1 << 4) | (1 << 8))) { + /* + * Either the link has failed, or we have + * a CRC error. + * Sometimes this can happen due to link + * retrain, so lets knock it down and see + * if its transient + */ + ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc + pci_write_config16(devx, pos + ctrl_off, ctrl); + ctrl = pci_read_config16(devx, pos + ctrl_off); + if (ctrl & ((1 << 4) | (1 << 8))) { + /* Can not clear the error */ + break; + } + } + } while ((ctrl & (1 << 5)) == 0); + + break; } - pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT); + pos = pci_s_find_next_capability(PCI_DEV(0,0,0), PCI_CAP_ID_HT, 0); } } while (last_unitid != next_unitid);