Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 11:
Well my quick analysis is that biggest time savings to achieve are the certain paths of vboot that are somewhat proportional to the size of the FMAP region verified. Reduce FSP blob size to achieve improvements there. As for the biggest single timestamped section, it appears to be FspSiliconInit... do less in FSP and you get to further reduce the FSP blob size. Replacement native coreboot code is likely to execute faster and take less space.
Yes, this was written with tongue in the cheek. Give us native raminit and source, and we'll likely throw out any UEFI and instantly take away 50+ ms from cold boots. Unless the figures against a solution with POSTCAR_STAGE=y show a much more significant improvement (4 ms of 830ms is <0.5 %) I see no value in the approach of skipping the separate POSTCAR_STAGE.