Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46260 )
Change subject: soc/intel/common: Add PCIe Runtime D3 driver for ACPI ......................................................................
Patch Set 15:
(5 comments)
https://review.coreboot.org/c/coreboot/+/46260/15/src/soc/intel/common/block... File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/46260/15/src/soc/intel/common/block... PS15, Line 33: OS to apply security restrictions.
This ties into external devices in general but there are some devices like SD-express which need bot […]
Ack.
https://review.coreboot.org/c/coreboot/+/46260/15/src/soc/intel/common/block... PS15, Line 44: Disable the ACPI-driven L23
I've been asking myself (and Intel) the same question. […]
Ack.
https://review.coreboot.org/c/coreboot/+/46260/15/src/soc/intel/common/block... File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/46260/15/src/soc/intel/common/block... PS15, Line 148: config->enable_gpio.pin_count
Ah I need to fix the comment in chip.h as I did end up making it optional. […]
Ack.
https://review.coreboot.org/c/coreboot/+/46260/15/src/soc/intel/common/block... PS15, Line 241: PCIE_HOTPLUG_IN_D3_UUID
This is the property that actually tells the kernel to run the _ON/_OFF methods on a hotplug root po […]
Ack.
https://review.coreboot.org/c/coreboot/+/46260/15/src/soc/intel/common/block... PS15, Line 281: PXSX
It is still pending backport into 5. […]
Aah I see. Sounds good.