Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), : /* GPP_A1 - LAD0 */ : _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), : /* GPP_A2 - LAD1 */ : _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), : /* GPP_A3 - LAD2 */ : _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), : /* GPP_A4 - LAD3 */ : _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), : /* GPP_A5 - LFRAME# */ : _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), : /* GPP_A6 - SERIRQ */ : _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), : /* GPP_A7 - PIRQA# */ : _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010),
so NF1/NF3 is automatically selected based on how board is strapped, eSPI vs LPC. […]
Yes you are right. These NFs are set automatically after a reset. But I'm not sure, the default settings are the same as mine in this patch.
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 24: RX_DISABLE We should check all the settings for the DW0 register. For example, the Tx and Rx buffer state. I think that the settings will be different, so we should leave this configuration as it is.