[coreboot-gerrit] Change in coreboot[master]: mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default value

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44452 )

Change subject: mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default value
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mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default value

On MT8192 the SPI flash is actually using a SPI-NOR controller with
its own bus. The number here should be a virtual value as
(SPI_BUS_NUMBER + 1).

Signed-off-by: CK Hu 
Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
Reviewed-by: Yu-Ping Wu 
---
M src/mainboard/google/asurada/Kconfig
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved
  Yu-Ping Wu: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig
index e1c96f0..f5ffb3c 100644
--- a/src/mainboard/google/asurada/Kconfig
+++ b/src/mainboard/google/asurada/Kconfig
@@ -41,9 +41,11 @@
    hex
    default 0x0

+# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus.
+# The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
 config BOOT_DEVICE_SPI_FLASH_BUS
    int
-	default 1
+	default 9

config EC_GOOGLE_CHROMEEC_SPI_BUS
    hex