[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne/fch: disable 48MHz output in S0i3

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60125

to look at the new patch set (#2).

Change subject: soc/amd/cezanne/fch: disable 48MHz output in S0i3
......................................................................

soc/amd/cezanne/fch: disable 48MHz output in S0i3

S0i3 is a low power state which reduces the power consumption to about
the level of the S3 suspend state where the DRAM is kept in a self-
refresh state and most of the rest of the system is powered down. So
everything that can be switched off in the S0i3 state should be switched
off in order to maximize the standby time.

BUG=b:210722314

Signed-off-by: Felix Held 
Change-Id: If445f5825dc7b795c95d73c061156cc485421ada
---
M src/soc/amd/cezanne/fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60125/2