[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81370?usp=email )

Change subject: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
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soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder

Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs.

TEST=intel/archercity CRB

Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370
Tested-by: build bot (Jenkins) 
Reviewed-by: Jincheng Li 
Reviewed-by: Shuo Liu 
---
M src/soc/intel/xeon_sp/ebg/Makefile.mk
R src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
R src/soc/intel/xeon_sp/ebg/soc_xhci.c
M src/soc/intel/xeon_sp/spr/Makefile.mk
M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
5 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Jincheng Li: Looks good to me, but someone else must approve
  Shuo Liu: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/ebg/Makefile.mk b/src/soc/intel/xeon_sp/ebg/Makefile.mk
index ac73acb..b05c05b 100644
--- a/src/soc/intel/xeon_sp/ebg/Makefile.mk
+++ b/src/soc/intel/xeon_sp/ebg/Makefile.mk
@@ -2,6 +2,6 @@

bootblock-y += soc_gpio.c soc_pch.c
 romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
-ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
+ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c

CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/xhci.h b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
similarity index 100%
rename from src/soc/intel/xeon_sp/spr/include/soc/xhci.h
rename to src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
diff --git a/src/soc/intel/xeon_sp/spr/xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c
similarity index 92%
rename from src/soc/intel/xeon_sp/spr/xhci.c
rename to src/soc/intel/xeon_sp/ebg/soc_xhci.c
index 544ea16..f8aa37b 100644
--- a/src/soc/intel/xeon_sp/spr/xhci.c
+++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c
@@ -2,10 +2,13 @@

#include <console/console.h>
 #include <device/pci.h>
-#include <soc/pci_devs.h>
+#include <soc/pch_pci_devs.h>
 #include <soc/xhci.h>
 #include <types.h>

+// XHCI register
+#define SYS_BUS_CFG2 0x44
+
 static uint8_t *get_xhci_bar(void)
 {
    const struct resource *res;
diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk
index 163b5ea..fc8ab17 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/spr/Makefile.mk
@@ -12,7 +12,7 @@
 romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c

-ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c
+ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c
 ramstage-y += crashlog.c ioat.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
index 09953aa..510a67f 100644
--- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
@@ -122,9 +122,6 @@
 #define IIO_DFX_TSWCTL0 0x30c
 #define IIO_DFX_LCK_CTL 0x504

-// XHCI register
-#define SYS_BUS_CFG2 0x44
-
 /* MSM registers */
 #define MSM_BUS 0xF2
 #define MSM_DEV 3