Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37346 )
Change subject: binaryPI: Clean leftover romstage prototype ......................................................................
binaryPI: Clean leftover romstage prototype
Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/cpu/amd/car.h M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/pcengines/apu2/romstage.c 7 files changed, 7 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37346/1
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 46f7e1d..be7b69a 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -3,8 +3,6 @@
#include <arch/cpu.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); - void *asmlinkage romstage_main(unsigned long bist);
#endif diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 32f52de..03e6585 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -19,11 +19,10 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val;
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 495ce59..2979cf4 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -19,13 +19,13 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ u32 val; +static void romstage_main_template(void) +{ + u32 val;
/* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 77a0ea0..67485f4 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -19,7 +19,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/common/amd_defs.h> @@ -28,7 +27,7 @@
#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val;
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6df12e3..5198258 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -19,12 +19,11 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val;
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 774cd99..4c5a51b 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -19,7 +19,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,7 +27,7 @@
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val;
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 4df1e47..8eb1818 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -21,7 +21,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h>