[coreboot-gerrit] Change in coreboot[master]: mainboard/ocp/monolake: Hide NIC IIO root ports earlier

[Andrey Petrov (Code Review)]

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35968 )

Change subject: mainboard/ocp/monolake: Hide NIC IIO root ports earlier
......................................................................

mainboard/ocp/monolake: Hide NIC IIO root ports earlier

It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. Because of that explicitly hide in romstage.

TEST=the patch was ran on affected HW and success was reported

Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov 
---
M src/mainboard/ocp/monolake/devicetree.cb
M src/mainboard/ocp/monolake/romstage.c
2 files changed, 9 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35968/1

diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb
index 26c95d5..6a8bef1 100644
--- a/src/mainboard/ocp/monolake/devicetree.cb
+++ b/src/mainboard/ocp/monolake/devicetree.cb
@@ -4,8 +4,6 @@
    end
    device domain 0 on
    	device pci 00.0 on end # SoC router
-		device pci 02.2 off end # IOU0 port C, 10GbE
-		device pci 02.3 off end # IOU0 port D, 10GbE
    	device pci 14.0 on end # xHCI Controller
    	device pci 19.0 on end # Gigabit LAN Controller
    	device pci 1d.0 on end # EHCI Controller
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
index ef41b77..4a1a235 100644
--- a/src/mainboard/ocp/monolake/romstage.c
+++ b/src/mainboard/ocp/monolake/romstage.c
@@ -26,7 +26,7 @@
 #include <soc/pci_devs.h>
 #include <soc/lpc.h>
 #include <soc/gpio.h>
-
+#include <soc/ubox.h>

/* Define the strings for UPD variables that could be customized */
 #define FSP_VAR_HYPERTHREADING "HyperThreading"
@@ -207,6 +207,14 @@
    	printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
    	full_reset();
    }
+
+	/*
+	 * Explicitly hide internal root port IIO devices that GbE device is connected to.
+	 * We can't use devicetree for this since FSP seemingly gets confused if we hide
+	 * after MemoryInit API was called.
+	 */
+	iio_hide(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2C_FUNC);
+	iio_hide(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2D_FUNC);
 }

/**