[coreboot-gerrit] Change in coreboot[master]: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for...

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35313 )

Change subject: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35313/2/src/northbridge/amd/pi/0073... 
File src/northbridge/amd/pi/00730F01/northbridge.c:

https://review.coreboot.org/c/coreboot/+/35313/2/src/northbridge/amd/pi/0073... 
PS2, Line 781: 0xB0
> E or B?

0xE0 is an index register that provides access to GPP link core registers 0x0140XXXX and IO Link Strap Control register has an offset of 00B0 which assembles to 0x014000B0