[coreboot-gerrit] Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init

[Patrick Rudolph (Code Review)]

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 )

Change subject: soc/intel/*: Update microcode as specified for MP-init
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Patch Set 13:

(1 comment)

File src/soc/intel/alderlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/49899/comment/ed0123ed_df660a68 
PS13, Line 70: PRMRR
> > For ADL, there is a new MCHECK flow in the FSP, which apparently requires a microcode load immedia […]

So with USE_INTEL_FSP_MP_INIT and (FSP_TEMP_RAM_INIT || MicroCodeRegionBase) FSP will do a second microcode update.
With CpuMpPpi this will (maybe) happen after coreboot's MPinit, so having a second reload here might be wrong?