[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3

[Kun Liu (Code Review)]

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79320?usp=email )

Change subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
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mb/google/rex/var/screebo: Add delay 1ms after Main 3V3

Add delay 1ms after Main 3V3

BUG=b:313976507
TEST=when S0ix returns S0, PERST needs to delay until
Main 3V3 is stable and then pull up

Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0
Signed-off-by: Kun Liu 
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79320/1

diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 8be0e85..9aa038e 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -289,6 +289,7 @@
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
    			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
+				register "enable_delay_ms" = "1"
    			register "srcclk_pin" = "6"
    			device generic 0 on
    				probe DB_SD SD_GL9750