[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/romstage: Do initial SoC commit till romstage

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45192 )

Change subject: soc/intel/alderlake/romstage: Do initial SoC commit till romstage
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Patch Set 9:

(1 comment)
> Patch Set 9: Code-Review+2
>
> (2 comments)
>
> LGTM.

Thanks Angel

https://review.coreboot.org/c/coreboot/+/45192/8/src/soc/intel/alderlake/rom... 
File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/45192/8/src/soc/intel/alderlake/rom... 
PS8, Line 69: /* DP port config */
            : 	m_cfg->DdiPortAConfig = config->DdiPortAConfig;
            : 	m_cfg->DdiPortBConfig = config->DdiPortBConfig;
            : 	m_cfg->DdiPortAHpd = config->DdiPortAHpd;
            : 	m_cfg->DdiPortBHpd = config->DdiPortBHpd;
            : 	m_cfg->DdiPortCHpd = config->DdiPortCHpd;
            : 	m_cfg->DdiPort1Hpd = config->DdiPort1Hpd;
            : 	m_cfg->DdiPort2Hpd = config->DdiPort2Hpd;
            : 	m_cfg->DdiPort3Hpd = config->DdiPort3Hpd;
            : 	m_cfg->DdiPort4Hpd = config->DdiPort4Hpd;
            : 	m_cfg->DdiPortADdc = config->DdiPortADdc;
            : 	m_cfg->DdiPortBDdc = config->DdiPortBDdc;
            : 	m_cfg->DdiPortCDdc = config->DdiPortCDdc;
            : 	m_cfg->DdiPort1Ddc = config->DdiPort1Ddc;
            : 	m_cfg->DdiPort2Ddc = config->DdiPort2Ddc;
            : 	m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
            : 	m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
> Welp. I think we can keep it like this for now. […]

agree, we need to find a way to skip all GPIO programming in FSP and let CB only do the same, will get back on this.