[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: add downcoring and SMT disable settings to devicetree

[Marshall Dawson (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Paul Menzel, Felix Held.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52197 )

Change subject: soc/amd/cezanne: add downcoring and SMT disable settings to devicetree
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Patch Set 3:

(2 comments)

File src/soc/amd/cezanne/chip.h:

https://review.coreboot.org/c/coreboot/+/52197/comment/5569b96b_5a6d1575 
PS1, Line 16: uint8_t
> Yup, same for picasso too.  AGESA sanity checks it BTW.

Felix, did you intend to change this too?

https://review.coreboot.org/c/coreboot/+/52197/comment/b5f41bc1_f2218cf5 
PS1, Line 16: disable_smt
> i added to the comment on downcore_mode that it's about physical cores; that in combination with the […]

I thought SMT is industry nomenclature for Symmetric MultiThreading aka hyperthreading, but were you asking for that commented too?