[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Update microcode before FSP

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, Huang Jin, Lee Leahy, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36198

to look at the new patch set (#2).

Change subject: soc/intel/braswell: Update microcode before FSP
......................................................................

soc/intel/braswell: Update microcode before FSP

The google FSP Braswell version has broken microcode update code and
FSP checks at some point if the installed microcode version is non
zero, so coreboot has to update it before calling FSP-T.

This is fixed with newer FSP releases by Intel, but doing updates
won't hurt.

Tested with both Intel FSP and google FSP.

Change-Id: I3e81329854e823dc66fec191adbed617bb37d649
Signed-off-by: Arthur Heymans 
---
M src/drivers/intel/fsp1_1/Makefile.inc
M src/drivers/intel/fsp1_1/cache_as_ram.S
2 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/36198/2